[Mlir-commits] [mlir] [mlir][Vector] Add support for trunci to narrow type emulation (PR #82565)

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git-clang-format --diff c63e68ba5fb54b69521c4f010d1c5290856c6509 f2021d70a7f5da5d29f5513c5c6b6df6090261f8 -- mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
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View the diff from clang-format here.
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diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 394041bd2b..a5fbd97e2b 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -914,10 +914,12 @@ static Value rewriteI8ToI4Trunc(PatternRewriter &rewriter, Location loc,
   VectorType deinterI8VecType = highShuffleOp.getResultVectorType();
   auto shiftValues = rewriter.create<arith::ConstantOp>(
       loc, DenseElementsAttr::get(deinterI8VecType, bitsToShift));
-  auto shlHighOp = rewriter.create<arith::ShLIOp>(loc, highShuffleOp, shiftValues);
+  auto shlHighOp =
+      rewriter.create<arith::ShLIOp>(loc, highShuffleOp, shiftValues);
 
   // 4. Merge high and low i4 values.
-  auto mergedHiLowOp = rewriter.create<arith::OrIOp>(loc, shlHighOp, lowShuffleOp);
+  auto mergedHiLowOp =
+      rewriter.create<arith::OrIOp>(loc, shlHighOp, lowShuffleOp);
 
   // 5. Generate a bitcast vector<Xxi8> -> vector<2Xxi4>.
   auto i4VecType = srcVecType.cloneWith(std::nullopt, rewriter.getI4Type());
@@ -1130,8 +1132,7 @@ struct RewriteAlignedSubByteIntTrunc : OpRewritePattern<arith::TruncIOp> {
     if (srcVecType.getRank() != 1)
       return failure();
 
-    if (failed(
-            commonConversionPrecondition(rewriter, srcVecType, truncOp)))
+    if (failed(commonConversionPrecondition(rewriter, srcVecType, truncOp)))
       return failure();
 
     // Check general alignment preconditions. We invert the src/dst type order
@@ -1143,7 +1144,8 @@ struct RewriteAlignedSubByteIntTrunc : OpRewritePattern<arith::TruncIOp> {
     // Create a new iX -> i8 truncation op.
     Location loc = truncOp.getLoc();
     auto i8VecType = srcVecType.cloneWith(std::nullopt, rewriter.getI8Type());
-    Value i8TruncVal = rewriter.create<arith::TruncIOp>(loc, i8VecType, srcValue);
+    Value i8TruncVal =
+        rewriter.create<arith::TruncIOp>(loc, i8VecType, srcValue);
 
     // Rewrite the i8 -> i4 truncation part.
     Value subByteTrunc = rewriteI8ToI4Trunc(rewriter, loc, i8TruncVal);
@@ -1154,7 +1156,6 @@ struct RewriteAlignedSubByteIntTrunc : OpRewritePattern<arith::TruncIOp> {
   }
 };
 
-
 /// Rewrite a sub-byte vector transpose into a sequence of instructions that
 /// perform the transpose on wider (byte) element types.
 /// For example:
@@ -1228,8 +1229,8 @@ void vector::populateVectorNarrowTypeRewritePatterns(
   // generate better performance for aligned cases.
   patterns.add<RewriteAlignedSubByteIntSignedExt<arith::ExtSIOp>,
                RewriteAlignedSubByteIntSignedExt<arith::SIToFPOp>,
-               RewriteAlignedSubByteIntTrunc>(
-      patterns.getContext(), benefit.getBenefit() + 1);
+               RewriteAlignedSubByteIntTrunc>(patterns.getContext(),
+                                              benefit.getBenefit() + 1);
 }
 
 void vector::populateVectorTransposeNarrowTypeRewritePatterns(

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https://github.com/llvm/llvm-project/pull/82565