[Mlir-commits] [mlir] [mlir][ArmSVE] Add intrinsics for the SME2 multi-vector zips (PR #80985)
Benjamin Maxwell
llvmlistbot at llvm.org
Thu Feb 8 07:05:10 PST 2024
================
@@ -314,3 +314,45 @@ llvm.func @arm_sve_convert_to_svbool(
: (vector<[1]xi1>) -> vector<[16]xi1>
llvm.return
}
+
+// CHECK-LABEL: arm_sve_zip_x2(
+// CHECK-SAME: <vscale x 16 x i8> %[[V1:[0-9]+]],
+// CHECK-SAME: <vscale x 8 x i16> %[[V2:[0-9]+]],
+// CHECK-SAME: <vscale x 4 x i32> %[[V3:[0-9]+]],
+// CHECK-SAME: <vscale x 2 x i64> %[[V4:[0-9]+]])
+llvm.func @arm_sve_zip_x2(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>, %nxv4i32: vector<[4]xi32>, %nxv2i64: vector<[2]xi64>) {
----------------
MacDue wrote:
I think they are, but as with all the other SVE intrinsics (and most intrinsics in general) the checking is very minimal. The higher level `arm_sve.zip.x4` and `arm_sve.zip.x2` will more rigorously check types.
https://github.com/llvm/llvm-project/pull/80985
More information about the Mlir-commits
mailing list