[Mlir-commits] [mlir] 2806705 - [MLIR][NVVM] Enable import of nvvm.barrier0 (#119965)

[llvmlistbot at llvm.org]

Author: Ivan R. Ivanov
Date: 2024-12-17T13:07:28+09:00
New Revision: 2806705c4bf69cbb1a8e482104efb9429bb50683

URL: https://github.com/llvm/llvm-project/commit/2806705c4bf69cbb1a8e482104efb9429bb50683
DIFF: https://github.com/llvm/llvm-project/commit/2806705c4bf69cbb1a8e482104efb9429bb50683.diff

LOG: [MLIR][NVVM] Enable import of nvvm.barrier0 (#119965)

Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    mlir/test/Target/LLVMIR/Import/nvvmir.ll

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
index 6f8971ca3c00c6..5d8772d9d5c5f5 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
@@ -117,14 +117,13 @@ class NVVM_Attr<string attrName, string attrMnemonic, list<Trait> traits = []>
 // NVVM intrinsic operations
 //===----------------------------------------------------------------------===//
 
-class NVVM_IntrOp<string mnem, list<Trait> traits,
-                  int numResults>
+class NVVM_IntrOp<string mnem, list<Trait> traits = [],
+                  int numResults = 0>
   : LLVM_IntrOpBase<NVVM_Dialect, mnem, "nvvm_" # !subst(".", "_", mnem),
                     /*list<int> overloadedResults=*/[],
                     /*list<int> overloadedOperands=*/[],
                     traits, numResults>;
 
-
 //===----------------------------------------------------------------------===//
 // NVVM special register op definitions
 //===----------------------------------------------------------------------===//
@@ -431,10 +430,7 @@ def NVVM_MBarrierTestWaitSharedOp : NVVM_Op<"mbarrier.test.wait.shared">,
 // NVVM synchronization op definitions
 //===----------------------------------------------------------------------===//
 
-def NVVM_Barrier0Op : NVVM_Op<"barrier0"> {
-  string llvmBuilder = [{
-      createIntrinsicCall(builder, llvm::Intrinsic::nvvm_barrier0);
-  }];
+def NVVM_Barrier0Op : NVVM_IntrOp<"barrier0"> {
   let assemblyFormat = "attr-dict";
 }
 

diff  --git a/mlir/test/Target/LLVMIR/Import/nvvmir.ll b/mlir/test/Target/LLVMIR/Import/nvvmir.ll
index 131e9065b2d883..c8b7b82f47fd93 100644
--- a/mlir/test/Target/LLVMIR/Import/nvvmir.ll
+++ b/mlir/test/Target/LLVMIR/Import/nvvmir.ll
@@ -71,12 +71,15 @@ define float @nvvm_rcp(float %0) {
   ret float %2
 }
 
-; TODO: Support the intrinsics below once they derive from NVVM_IntrOp rather than from NVVM_Op.
+; CHECK-LABEL: @llvm_nvvm_barrier0()
+define void @llvm_nvvm_barrier0() {
+  ; CHECK: nvvm.barrier0
+  call void @llvm.nvvm.barrier0()
+  ret void
+}
 
-; define void @llvm_nvvm_barrier0() {
-;   call void @llvm.nvvm.barrier0()
-;   ret void
-; }
+
+; TODO: Support the intrinsics below once they derive from NVVM_IntrOp rather than from NVVM_Op.
 ;
 ; define i32 @nvvm_shfl(i32 %0, i32 %1, i32 %2, i32 %3, float %4) {
 ;   %6 = call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 %0, i32 %3, i32 %1, i32 %2)