[Mlir-commits] [mlir] [MLIR] Implement emulation of static indexing subbyte type vector stores (PR #115922)

[Andrzej Warzyński]

banach-space wrote:

Thank you for your reply!

> Should we allow vector.load to be atomic? I do think in some cases we don't but in some other extreme cases we might need it to be bug-free.

Let me rephrase my question - is there something inherently different between `vector.store` and `vector.load` that makes one better (or more desirable) for atomic accesses? In essence, in both cases "emulation" leads to some decomposition into finer grain "access" Ops (either load or store), right? In fact, I could take your example from the summary and reverse it (load `vector<7xi2>` from `memref<3x7xi2>[1, 0]`). So what makes `vector.store` special? Apologies if I'm missing something obvious here 🤔 

> But for now, we haven't encountered a case where this is necessary. So... maybe a future improvement?

Absolutely no need to implement it if you don't need it. However, it would still be good to document what the current support is and mark the outstanding features as TODOs. Especially when the support for `vector.store` and `vector.load` is non-symmetric.

https://github.com/llvm/llvm-project/pull/115922