[Mlir-commits] [mlir] a9eb8f0 - [mlir][ArmSME] Fix crash on empty vector.mask in arm-sme-vector-legalization (#118613)

llvmlistbot at llvm.org llvmlistbot at llvm.org
Thu Dec 5 00:48:33 PST 2024


Author: Benjamin Maxwell
Date: 2024-12-05T08:48:30Z
New Revision: a9eb8f0e3dbaf16b6bd83eecb960b6ea8ecaa8c3

URL: https://github.com/llvm/llvm-project/commit/a9eb8f0e3dbaf16b6bd83eecb960b6ea8ecaa8c3
DIFF: https://github.com/llvm/llvm-project/commit/a9eb8f0e3dbaf16b6bd83eecb960b6ea8ecaa8c3.diff

LOG: [mlir][ArmSME] Fix crash on empty vector.mask in arm-sme-vector-legalization (#118613)

Fixes #118449

Added: 
    

Modified: 
    mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
    mlir/test/Dialect/ArmSME/vector-legalization.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp b/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
index e908a536e6fb27..61767f3b21c9c3 100644
--- a/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
+++ b/mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
@@ -265,8 +265,8 @@ struct LegalizeMaskedVectorOuterProductOpsByDecomposition
   LogicalResult
   matchAndRewrite(vector::MaskOp maskOp, OpAdaptor adaptor,
                   OneToNPatternRewriter &rewriter) const override {
-    if (auto outerProductOp =
-            llvm::dyn_cast<vector::OuterProductOp>(maskOp.getMaskableOp())) {
+    if (auto outerProductOp = llvm::dyn_cast_or_null<vector::OuterProductOp>(
+            maskOp.getMaskableOp())) {
       LegalizeVectorOuterProductOpsByDecomposition pattern(*getTypeConverter(),
                                                            getContext());
       return static_cast<RewritePattern &>(pattern).matchAndRewrite(

diff  --git a/mlir/test/Dialect/ArmSME/vector-legalization.mlir b/mlir/test/Dialect/ArmSME/vector-legalization.mlir
index 458906a1879829..d56df9814f1733 100644
--- a/mlir/test/Dialect/ArmSME/vector-legalization.mlir
+++ b/mlir/test/Dialect/ArmSME/vector-legalization.mlir
@@ -646,3 +646,13 @@ func.func @negative_transpose_store_scalable_via_za__bad_source_shape(%vec: vect
   vector.transfer_write %tr, %dest[%i, %j] {in_bounds = [true, true]} : vector<[7]x2xf32>,  memref<?x?xf32>
   return
 }
+
+// -----
+
+// From: https://github.com/llvm/llvm-project/issues/118449.
+// Check -arm-sme-vector-legalization does not crash when it encounters a `vector.mask` that
+// does not contain a maskable op.
+func.func @vector_mask_without_maskable_op(%mask: vector<16x2xi1>, %vec: vector<16x16xf32>) -> vector<16x16xf32> {
+  %0 = vector.mask %mask { vector.yield %vec : vector<16x16xf32> } : vector<16x2xi1> -> vector<16x16xf32>
+  return %0 : vector<16x16xf32>
+}


        


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