[Mlir-commits] [mlir] [mlir][Vector] Support mixed mode vector.contract lowering (PR #117753)

[Kunwar Grover]

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@@ -80,6 +80,22 @@ static AffineMap adjustMap(AffineMap map, int64_t index,
   return AffineMap::get(map.getNumDims() - 1, 0, results, ctx);
 }
 
+Value promoteToElementType(Location loc, RewriterBase &rewriter, Value v,
+                           Type dstElementType) {
+  Type elementType = v.getType();
+  auto vecType = dyn_cast<VectorType>(elementType);
+  if (vecType)
+    elementType = vecType.getElementType();
+  if (elementType == dstElementType)
+    return v;
+  Type promotedType = dstElementType;
+  if (vecType)
+    promotedType = vecType.clone(promotedType);
+  if (isa<FloatType>(dstElementType))
+    return rewriter.create<arith::ExtFOp>(loc, promotedType, v);
+  return rewriter.create<arith::ExtSIOp>(loc, promotedType, v);
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Groverkss wrote:

>From vector.contract docs:

> If operands and the result have types of different bitwidths, operands are promoted to have the same bitwidth as the result before performing the contraction. For integer types, only signless integer types are supported, and the promotion happens via sign extension.

I will add a comment here.

https://github.com/llvm/llvm-project/pull/117753