[Mlir-commits] [llvm] [mlir] Add usub_cond and usub_sat operations to atomicrmw (PR #105568)

[Matt Arsenault]

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@@ -41,6 +41,8 @@ bool isIdempotentRMW(AtomicRMWInst& RMWI) {
     case AtomicRMWInst::Sub:
     case AtomicRMWInst::Or:
     case AtomicRMWInst::Xor:
+    case AtomicRMWInst::USubCond:
+    case AtomicRMWInst::USubSat:
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arsenm wrote:

Missing tests for this (I would also split the instcombine piece into a separate change) 

https://github.com/llvm/llvm-project/pull/105568