[Mlir-commits] [mlir] [MLIR][AMDGPU] Introduce fp16 packed arithmetic (PR #105688)

[Krzysztof Drewniak]

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@@ -272,17 +289,96 @@ void TruncFToFloat8RewritePattern::rewrite(arith::TruncFOp op,
   rewriter.replaceOp(op, result);
 }
 
+LogicalResult TruncfToFloat16RewritePattern::match(arith::TruncFOp op) const {
+  Type outType = op.getOut().getType();
+  Type inputType = getElementTypeOrSelf(op.getIn());
+  if (auto outVecType = dyn_cast<VectorType>(outType)) {
+    if (outVecType.isScalable())
+      return failure();
+    if (outVecType.getShape().size() > 1)
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krzysz00 wrote:

Please copy multi-dimensional vector support from existing patterns

https://github.com/llvm/llvm-project/pull/105688