[Mlir-commits] [mlir] [mlir][vector] Refactor vector-transfer-to-vector-load-store.mlir (NFC) (PR #105509)

[Pablo Antonio Martinez]

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@@ -331,53 +331,52 @@ func.func @transfer_read_permutations(%arg0 : memref<?x?xf32>, %arg1 : memref<?x
 }
 
 // CHECK-LABEL: func @transfer_write_permutations
-// CHECK-SAME:      %[[ARG0:.*]]: memref<?x?x?x?xf32>
-// CHECK-SAME:      %[[ARG1:.*]]: tensor<?x?x?x?xf32>
-// CHECK-SAME:      %[[ARG2:.*]]: vector<7x14x8x16xf32>
-// CHECK-SAME:      %[[ARG3:.*]]: vector<8x16xf32>
-// CHECK-SAME:      %[[M:.*]]: i1
+// CHECK-SAME:    %[[MEM0:.*]]: memref<?x?x?x?xf32>
+// CHECK-SAME:    %[[ARG1:.*]]: tensor<?x?x?x?xf32>
+// CHECK-SAME:    %[[VEC0:.*]]: vector<7x14x8x16xf32>
+// CHECK-SAME:    %[[VEC1:.*]]: vector<8x16xf32>
+// CHECK-SAME:    %[[M:.*]]: i1
 func.func @transfer_write_permutations(
-    %arg0 : memref<?x?x?x?xf32>, %arg1 : tensor<?x?x?x?xf32>,
-    %v1 : vector<7x14x8x16xf32>, %v2 : vector<8x16xf32>, %m: i1) -> tensor<?x?x?x?xf32> {
+    %mem_0 : memref<?x?x?x?xf32>, %arg1 : tensor<?x?x?x?xf32>,
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pabloantoniom wrote:

I also found weird the %arg1 and %mem mix. I have renamed vector arguments as %src as suggested.

Regarding the test, I have split it into two different tests, `transfer_write_permutations_tensor` and `transfer_write_permutations_memref`. I took extra care not to miss anything but please have a careful look when reviewing as well to make sure the split is correct. Thanks 👍 

https://github.com/llvm/llvm-project/pull/105509