[Mlir-commits] [mlir] [mlir][emitc] Add 'emitc.switch' op to the dialect (PR #102331)

[Gil Rapaport]

================
@@ -1096,6 +1101,198 @@ GetGlobalOp::verifySymbolUses(SymbolTableCollection &symbolTable) {
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// SwitchOp
+//===----------------------------------------------------------------------===//
+
+/// Parse the case regions and values.
+static ParseResult
+parseSwitchCases(OpAsmParser &parser, DenseI64ArrayAttr &cases,
+                 SmallVectorImpl<std::unique_ptr<Region>> &caseRegions) {
+  SmallVector<int64_t> caseValues;
+  while (succeeded(parser.parseOptionalKeyword("case"))) {
+    int64_t value;
+    Region &region = *caseRegions.emplace_back(std::make_unique<Region>());
+
+    if (parser.parseInteger(value) || parser.parseColon() ||
+        parser.parseRegion(region, /*arguments=*/{}))
+      return failure();
+    caseValues.push_back(value);
+  }
+  cases = parser.getBuilder().getDenseI64ArrayAttr(caseValues);
+  return success();
+}
+
+/// Print the case regions and values.
+static void printSwitchCases(OpAsmPrinter &p, Operation *op,
+                             DenseI64ArrayAttr cases, RegionRange caseRegions) {
+  for (auto [value, region] : llvm::zip(cases.asArrayRef(), caseRegions)) {
+    p.printNewline();
+    p << "case " << value << ": ";
+    p.printRegion(*region, /*printEntryBlockArgs=*/false);
+  }
+}
+
+ParseResult SwitchOp::parse(OpAsmParser &parser, OperationState &result) {
+  OpAsmParser::UnresolvedOperand arg;
+  DenseI64ArrayAttr casesAttr;
+  SmallVector<std::unique_ptr<Region>, 2> caseRegionsRegions;
+  std::unique_ptr<Region> defaultRegionRegion = std::make_unique<Region>();
+
+  if (parser.parseOperand(arg))
+    return failure();
+
+  Type argType;
+  // Parse the case's type.
+  if (parser.parseColon() || parser.parseType(argType))
+    return failure();
+
+  auto loc = parser.getCurrentLocation();
+  if (parser.parseOptionalAttrDict(result.attributes))
+    return failure();
+
+  if (failed(verifyInherentAttrs(result.name, result.attributes, [&]() {
+        return parser.emitError(loc)
+               << "'" << result.name.getStringRef() << "' op ";
+      })))
+    return failure();
+
+  auto odsResult = parseSwitchCases(parser, casesAttr, caseRegionsRegions);
+  if (odsResult)
+    return failure();
+
+  result.getOrAddProperties<SwitchOp::Properties>().cases = casesAttr;
+
+  if (parser.parseKeyword("default") || parser.parseColon())
+    return failure();
+
+  if (parser.parseRegion(*defaultRegionRegion))
+    return failure();
+
+  result.addRegion(std::move(defaultRegionRegion));
+  result.addRegions(caseRegionsRegions);
+
+  if (parser.resolveOperand(arg, argType, result.operands))
+    return failure();
+
+  return success();
+}
+
+void SwitchOp::print(OpAsmPrinter &p) {
+  p << ' ';
+  p << getArg();
+  SmallVector<StringRef, 2> elidedAttrs;
+  elidedAttrs.push_back("cases");
+  p.printOptionalAttrDict((*this)->getAttrs(), elidedAttrs);
+  p << ' ';
+  printSwitchCases(p, *this, getCasesAttr(), getCaseRegions());
+  p.printNewline();
+  p << "default";
+  p << ' ';
+  p.printRegion(getDefaultRegion(), /*printEntryBlockArgs=*/true,
+                /*printBlockTerminators=*/true);
+}
+
+static LogicalResult verifyRegion(emitc::SwitchOp op, Region &region,
+                                  const Twine &name) {
+  auto yield = dyn_cast<emitc::YieldOp>(region.front().back());
+  if (!yield)
+    return op.emitOpError("expected region to end with emitc.yield, but got ")
+           << region.front().back().getName();
+
+  if (yield.getNumOperands() != 0) {
+    return (op.emitOpError("expected each region to return ")
+            << "0 values, but " << name << " returns "
+            << yield.getNumOperands())
+               .attachNote(yield.getLoc())
+           << "see yield operation here";
+  }
+  return success();
----------------
aniragil wrote:

nit: please add an empty line above.

https://github.com/llvm/llvm-project/pull/102331