[Mlir-commits] [mlir] [MLIR][GPU-LLVM] Convert `gpu.func` to `llvm.func` (PR #101664)
Jakub Kuderski
llvmlistbot at llvm.org
Fri Aug 2 08:36:13 PDT 2024
================
@@ -377,3 +377,288 @@ gpu.module @shuffles_mismatch {
return
}
}
+
+// -----
+
+gpu.module @kernels {
+// CHECK: llvm.func spir_funccc @no_kernel() {
+ gpu.func @no_kernel() {
+ gpu.return
+ }
+
+// CHECK: llvm.func spir_kernelcc @kernel_no_arg() attributes {gpu.kernel} {
+ gpu.func @kernel_no_arg() kernel {
+ gpu.return
+ }
+
+// CHECK: llvm.func spir_kernelcc @kernel_with_args(%[[VAL_0:.*]]: f32, %[[VAL_1:.*]]: i64) attributes {gpu.kernel} {
+ gpu.func @kernel_with_args(%arg0: f32, %arg1: i64) kernel {
+ gpu.return
+ }
+
+// CHECK-64: llvm.func spir_kernelcc @kernel_with_conv_args(%[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: !llvm.ptr, %[[VAL_4:.*]]: !llvm.ptr, %[[VAL_5:.*]]: i64) attributes {gpu.kernel} {
+// CHECK-32: llvm.func spir_kernelcc @kernel_with_conv_args(%[[VAL_2:.*]]: i32, %[[VAL_3:.*]]: !llvm.ptr, %[[VAL_4:.*]]: !llvm.ptr, %[[VAL_5:.*]]: i32) attributes {gpu.kernel} {
+ gpu.func @kernel_with_conv_args(%arg0: index, %arg1: memref<index>) kernel {
+ gpu.return
+ }
+
+// CHECK-64: llvm.func spir_kernelcc @kernel_with_sized_memref(%[[VAL_6:.*]]: !llvm.ptr, %[[VAL_7:.*]]: !llvm.ptr, %[[VAL_8:.*]]: i64, %[[VAL_9:.*]]: i64, %[[VAL_10:.*]]: i64) attributes {gpu.kernel} {
+// CHECK-32: llvm.func spir_kernelcc @kernel_with_sized_memref(%[[VAL_6:.*]]: !llvm.ptr, %[[VAL_7:.*]]: !llvm.ptr, %[[VAL_8:.*]]: i32, %[[VAL_9:.*]]: i32, %[[VAL_10:.*]]: i32) attributes {gpu.kernel} {
+ gpu.func @kernel_with_sized_memref(%arg0: memref<1xindex>) kernel {
+ gpu.return
+ }
+
+// CHECK-64: llvm.func spir_kernelcc @kernel_with_ND_memref(%[[VAL_11:.*]]: !llvm.ptr, %[[VAL_12:.*]]: !llvm.ptr, %[[VAL_13:.*]]: i64, %[[VAL_14:.*]]: i64, %[[VAL_15:.*]]: i64, %[[VAL_16:.*]]: i64, %[[VAL_17:.*]]: i64, %[[VAL_18:.*]]: i64, %[[VAL_19:.*]]: i64) attributes {gpu.kernel} {
+// CHECK-32: llvm.func spir_kernelcc @kernel_with_ND_memref(%[[VAL_11:.*]]: !llvm.ptr, %[[VAL_12:.*]]: !llvm.ptr, %[[VAL_13:.*]]: i32, %[[VAL_14:.*]]: i32, %[[VAL_15:.*]]: i32, %[[VAL_16:.*]]: i32, %[[VAL_17:.*]]: i32, %[[VAL_18:.*]]: i32, %[[VAL_19:.*]]: i32) attributes {gpu.kernel} {
+ gpu.func @kernel_with_ND_memref(%arg0: memref<128x128x128xindex>) kernel {
+ gpu.return
+ }
+}
+
+// -----
+
+gpu.module @kernels {
+// CHECK-LABEL: llvm.func spir_kernelcc @kernel_with_private_attribs(
----------------
kuhar wrote:
Do we care about the exact instruction sequence for memref ops? Perhaps this could be tested separately from the lowering for gpu.func?
https://github.com/llvm/llvm-project/pull/101664
More information about the Mlir-commits
mailing list