[Mlir-commits] [mlir] a3af099 - [mlir][NFC] Fix comment explaining ConverVectorLoad (#67864)

[llvmlistbot at llvm.org]

Author: tyb0807
Date: 2023-09-30T00:52:05+02:00
New Revision: a3af099785d5cf640dc2eca5d5c57bf9e3993a66

URL: https://github.com/llvm/llvm-project/commit/a3af099785d5cf640dc2eca5d5c57bf9e3993a66
DIFF: https://github.com/llvm/llvm-project/commit/a3af099785d5cf640dc2eca5d5c57bf9e3993a66.diff

LOG: [mlir][NFC] Fix comment explaining ConverVectorLoad (#67864)

The new number of elements should be the original one divided by a scale
factor computed from old and new bit width.

Added: 
    

Modified: 
    mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 6a186ae67eaa676..94300291dcd7d23 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -67,7 +67,7 @@ struct ConvertVectorLoad final : OpConversionPattern<vector::LoadOp> {
     //
     // can be replaced with
     //
-    // %1 = vector.load %0[%linear_index] : memref<12xi8>, vector<2xi8>
+    // %1 = vector.load %0[%linear_index] : memref<6xi8>, vector<2xi8>
     // %2 = vector.bitcast %1 : vector<2xi8> to vector<4xi4>
     //
     // TODO: Currently, only the even number of elements loading is supported.