[Mlir-commits] [mlir] 23b5f92 - [mlir][SME] Re-order patterns alphabetically (nfc)

[Andrzej Warzynski]

Author: Andrzej Warzynski
Date: 2023-09-29T16:54:47Z
New Revision: 23b5f92c97971dc7af27dc218c0f7f88c25da33f

URL: https://github.com/llvm/llvm-project/commit/23b5f92c97971dc7af27dc218c0f7f88c25da33f
DIFF: https://github.com/llvm/llvm-project/commit/23b5f92c97971dc7af27dc218c0f7f88c25da33f.diff

LOG: [mlir][SME] Re-order patterns alphabetically (nfc)

Added: 
    

Modified: 
    mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
    mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp

Removed: 
    


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diff  --git a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
index 6f95c8eb6b4264f..cbc5e468c729372 100644
--- a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
+++ b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
@@ -431,9 +431,8 @@ struct TransposeOpToArmSMELowering
 
 void mlir::populateVectorToArmSMEPatterns(RewritePatternSet &patterns,
                                           MLIRContext &ctx) {
-  patterns.add<TransferReadPermutationToArmSMELowering,
-               TransferWriteToArmSMELowering, VectorLoadToArmSMELowering,
-               VectorStoreToArmSMELowering, ConstantOpToArmSMELowering,
-               BroadcastOpToArmSMELowering, SplatOpToArmSMELowering,
-               TransposeOpToArmSMELowering>(&ctx);
+  patterns.add<BroadcastOpToArmSMELowering, ConstantOpToArmSMELowering,
+               SplatOpToArmSMELowering, TransferReadPermutationToArmSMELowering,
+               TransferWriteToArmSMELowering, TransposeOpToArmSMELowering,
+               VectorLoadToArmSMELowering, VectorStoreToArmSMELowering>(&ctx);
 }

diff  --git a/mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp b/mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
index 0322c2f3fcd14d4..e75e958e18a2cfd 100644
--- a/mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
+++ b/mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
@@ -600,10 +600,9 @@ void mlir::configureArmSMELegalizeForExportTarget(
 
 void mlir::populateArmSMELegalizeForLLVMExportPatterns(
     LLVMTypeConverter &converter, RewritePatternSet &patterns) {
-  patterns.add<EnableZAPattern, DisableZAPattern>(patterns.getContext());
-  patterns
-      .add<ZeroOpConversion, StoreTileSliceToArmSMELowering,
-           LoadTileSliceToArmSMELowering, MoveTileSliceToVectorArmSMELowering,
-           MoveVectorToTileSliceToArmSMELowering,
-           VectorOuterProductToArmSMELowering>(converter);
+  patterns.add<DisableZAPattern, EnableZAPattern>(patterns.getContext());
+  patterns.add<
+      LoadTileSliceToArmSMELowering, MoveTileSliceToVectorArmSMELowering,
+      MoveVectorToTileSliceToArmSMELowering, StoreTileSliceToArmSMELowering,
+      VectorOuterProductToArmSMELowering, ZeroOpConversion>(converter);
 }