[Mlir-commits] [mlir] 159e94a - [mlir][linalg][transform] Add some debug output to vectorization. (NFC) (#66520)

[llvmlistbot at llvm.org]

Author: Ingo Müller
Date: 2023-09-19T10:34:24+02:00
New Revision: 159e94a0c348043ce461512b5ba2e69e3cf81776

URL: https://github.com/llvm/llvm-project/commit/159e94a0c348043ce461512b5ba2e69e3cf81776
DIFF: https://github.com/llvm/llvm-project/commit/159e94a0c348043ce461512b5ba2e69e3cf81776.diff

LOG: [mlir][linalg][transform] Add some debug output to vectorization. (NFC) (#66520)

This helps to understand what the problem is when vectorization of
structured ops failes due to mismatching vector sizes.

Added: 
    

Modified: 
    mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
index f873bd0e0b68e43..51a83c35e4cda09 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
@@ -924,7 +924,6 @@ getTensorExtractMemoryAccessPattern(tensor::ExtractOp extractOp,
       targetShape.back() == 1)
     return VectorMemoryAccessKind::Gather;
 
-
   // 2. Assume that it's a gather load when reading _from_ a tensor for which
   // the trailing dimension is 1, e.g. `tensor<1x4x1xi32>`.
   // TODO: Relax this condition.
@@ -1484,6 +1483,10 @@ static LogicalResult vectorizeDynamicLinalgOpPrecondition(linalg::LinalgOp op) {
 static LogicalResult
 isValidMaskedInputVector(ArrayRef<int64_t> shape,
                          ArrayRef<int64_t> inputVectorSizes) {
+  LDBG("Iteration space static sizes:");
+  LLVM_DEBUG(llvm::interleaveComma(shape, llvm::dbgs()));
+  LLVM_DEBUG(llvm::dbgs() << "\n");
+
   if (inputVectorSizes.size() != shape.size()) {
     LDBG("Input vector sizes don't match the number of loops");
     return failure();