[Mlir-commits] [mlir] [mlir][spirv] Add support for VectorAnyINTEL capability (PR #68034)

[Lei Zhang]

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@@ -4146,7 +4146,12 @@ def SPIRV_Int32 : TypeAlias<I32, "Int32">;
 def SPIRV_Float32 : TypeAlias<F32, "Float32">;
 def SPIRV_Float : FloatOfWidths<[16, 32, 64]>;
 def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>;
-def SPIRV_Vector : VectorOfLengthAndType<[2, 3, 4, 8, 16],
+// Remove the vector size restriction.
+// Although the vector size can be upto (2^64-1), uint64,
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antiagainst wrote:

How does this actually work out for sizes > uint32 range? In SPIR-V the `OpTypeVector`'s component count is spec'ed to be a unsigned 32-bit integer.. Did the Intel spec somehow change the definition there? Could you point me to the spec?

https://github.com/llvm/llvm-project/pull/68034