[Mlir-commits] [mlir] [mlir][Vector] Fix integration test for vector.maskedload narrow type… (PR #70431)
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llvmlistbot at llvm.org
Fri Oct 27 02:13:20 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: None (tyb0807)
<details>
<summary>Changes</summary>
… emulation
Currently the expected CHECK values are not correct for `fcst_maskedload` from mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir
---
Full diff: https://github.com/llvm/llvm-project/pull/70431.diff
1 Files Affected:
- (modified) mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir (+1-1)
``````````diff
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir b/mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir
index 3c8c8d45013dc82..a0b39a2b68f4388 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/test-rewrite-narrow-types.mlir
@@ -206,7 +206,7 @@ func.func @entry() {
%passthru = arith.constant dense<[7, 8, 9, 10, 11, 12]> : vector<6xi4>
%load = call @fcst_maskedload(%A, %passthru) : (memref<?xi4>, vector<6xi4>) -> (vector<6xi4>)
vector.print %load : vector<6xi4>
- // CHECK: ( 1, 2, 3, -6, -5, -4 )
+ // CHECK: ( 0, 1, 2, -6, -5, -4 )
memref.dealloc %A : memref<?xi4>
return
``````````
</details>
https://github.com/llvm/llvm-project/pull/70431
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