[Mlir-commits] [mlir] [mlir][Vector] Add narrow type emulation pattern for vector.maskedload (PR #68443)
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Thu Oct 26 16:58:14 PDT 2023
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
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You can test this locally with the following command:
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git-clang-format --diff 7fe29e585723c8a90e798b3d852f2c54efb6f5dd 5172954c5e9a048f2429d72b1312a6e2c3ce4367 -- mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
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View the diff from clang-format here.
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diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 6e816c109..17ea44080 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -260,37 +260,42 @@ struct ConvertVectorMaskedLoad final
auto bitCast =
rewriter.create<vector::BitCastOp>(loc, op.getType(), newLoad);
- auto select =
- rewriter.create<arith::SelectOp>(loc, op.getMask(), bitCast, op.getPassThru());
+ auto select = rewriter.create<arith::SelectOp>(loc, op.getMask(), bitCast,
+ op.getPassThru());
rewriter.replaceOp(op, select->getResult(0));
-// // Setting the part that originally was not effectively loaded from memory
-// // to 0.
-// auto andMask = rewriter.create<arith::ExtSIOp>(loc, origType, op.getMask());
-// auto bitCastedAndMask =
-// rewriter.create<vector::BitCastOp>(loc, newType, andMask);
-// auto loadedFromMem =
-// rewriter.create<arith::AndIOp>(loc, newLoad, bitCastedAndMask);
-
-// // Copying from pass through.
-// auto allOne = rewriter.create<arith::ConstantOp>(
-// loc, origType,
-// DenseIntElementsAttr::get(origType, {APInt::getAllOnes(srcBits)}));
-// auto passThruMask = rewriter.create<arith::XOrIOp>(loc, allOne.getResult(),
-// andMask.getResult());
-// auto bitCastedPassThruMask =
-// rewriter.create<vector::BitCastOp>(loc, newType, passThruMask);
-// auto copiedFromPassThru =
-// rewriter.create<arith::AndIOp>(loc, newPassThru, bitCastedPassThruMask);
-
-// // Or-ing the first part loaded from memory and the second one copied from
-// // pass through to form the result.
-// auto result =
-// rewriter.create<arith::OrIOp>(loc, loadedFromMem, copiedFromPassThru);
-// auto bitCast =
-// rewriter.create<vector::BitCastOp>(loc, op.getType(), result);
-
-// rewriter.replaceOp(op, bitCast->getResult(0));
+ // // Setting the part that originally was not effectively loaded from
+ // memory
+ // // to 0.
+ // auto andMask = rewriter.create<arith::ExtSIOp>(loc, origType,
+ // op.getMask()); auto bitCastedAndMask =
+ // rewriter.create<vector::BitCastOp>(loc, newType, andMask);
+ // auto loadedFromMem =
+ // rewriter.create<arith::AndIOp>(loc, newLoad, bitCastedAndMask);
+
+ // // Copying from pass through.
+ // auto allOne = rewriter.create<arith::ConstantOp>(
+ // loc, origType,
+ // DenseIntElementsAttr::get(origType, {APInt::getAllOnes(srcBits)}));
+ // auto passThruMask = rewriter.create<arith::XOrIOp>(loc,
+ // allOne.getResult(),
+ // andMask.getResult());
+ // auto bitCastedPassThruMask =
+ // rewriter.create<vector::BitCastOp>(loc, newType, passThruMask);
+ // auto copiedFromPassThru =
+ // rewriter.create<arith::AndIOp>(loc, newPassThru,
+ // bitCastedPassThruMask);
+
+ // // Or-ing the first part loaded from memory and the second one copied
+ // from
+ // // pass through to form the result.
+ // auto result =
+ // rewriter.create<arith::OrIOp>(loc, loadedFromMem,
+ // copiedFromPassThru);
+ // auto bitCast =
+ // rewriter.create<vector::BitCastOp>(loc, op.getType(), result);
+
+ // rewriter.replaceOp(op, bitCast->getResult(0));
return success();
}
};
``````````
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https://github.com/llvm/llvm-project/pull/68443
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