[Mlir-commits] [mlir] [mlir][ArmSME] Update tile slice layout syntax (PR #69151)

Cullen Rhodes llvmlistbot at llvm.org
Mon Oct 16 02:40:18 PDT 2023


c-rhodes wrote:

> > > > The reason for this change is the current format doesn't play nicely with additional optional operands, required to support padding and masking (https://github.com/llvm/llvm-project/pull/69148), as it becomes ambiguous.
> > > 
> > > 
> > > Could you provide an example? Just to satisfy my curiosity. Ta!
> > 
> > 
> > See [b99b39b](https://github.com/llvm/llvm-project/commit/b99b39b6ab62c65b50bbfdc1a45b9bd3306fc4f9) which is adding optional padding and mask operands to `arm_sme.tile_load`. The assembly format is updated to add these, with the current layout format it would be:
> > ```
> >   let assemblyFormat =
> >     "$base `[` $indices `]` (`,` $padding `,` $mask^)? (`,` $layout^)?"
> >       "attr-dict `:` type($base) `,` type($result)";
> > ```
> > 
> > 
> > which is ambiguous. This adds the `layout` prefix so it isn't so, which is actually consistent with other optional attributes (e.g. fastmath)
> 
> So the change would be:
> 
> ```
>   // BEFORE
>   %tile_update = arm_sme.load_tile_slice %src[%c0], %tile, %tile_slice_index, <vertical> : memref<?x?xi8>, vector<[16]x[16]xi8>
>   // AFTER
>   %tile_update = arm_sme.load_tile_slice %src[%c0], %mask, %tile, %tile_slice_index layout<vertical> : memref<?x?xi8>, vector<[16]xi1>, vector<[16]x[16]xi8>
> ```
> 
> I don't quite see the ambiguity, but do prefer the more verbose/explicit form anyway :)

the ambiguity comes from having 2 optional groups with leading `,`, the generator can't handle this.

https://github.com/llvm/llvm-project/pull/69151


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