[Mlir-commits] [clang] [mlir] [llvm] [llvm][TypeSize] Consider TypeSize of '0' to be fixed/scalable-agnostic. (PR #72994)

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git-clang-format --diff 49f0070237709a979905d8fe823f47a1b0ebd8ee 674ade1adf2f66d81c8bf940479798a78ab32cb8 -- clang/lib/CodeGen/CGGPUBuiltin.cpp llvm/include/llvm/Analysis/TargetTransformInfoImpl.h llvm/include/llvm/CodeGen/BasicTTIImpl.h llvm/include/llvm/CodeGen/LowLevelType.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/include/llvm/IR/DataLayout.h llvm/include/llvm/Support/TypeSize.h llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h llvm/lib/Analysis/BasicAliasAnalysis.cpp llvm/lib/Analysis/Local.cpp llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/CodeGen/StackProtector.cpp llvm/lib/CodeGen/ValueTypes.cpp llvm/lib/IR/DataLayout.cpp llvm/lib/IR/DebugInfo.cpp llvm/lib/IR/Type.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMTargetTransformInfo.h llvm/lib/Target/DirectX/CBufferDataLayout.cpp llvm/lib/Target/Hexagon/HexagonISelLowering.cpp llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp llvm/lib/Target/VE/VETargetTransformInfo.h llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86TargetTransformInfo.cpp llvm/lib/Transforms/Coroutines/CoroFrame.cpp llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp llvm/lib/Transforms/Utils/Local.cpp llvm/unittests/CodeGen/LowLevelTypeTest.cpp llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp llvm/unittests/IR/InstructionsTest.cpp llvm/unittests/Support/TypeSizeTest.cpp mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
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diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
index 0c7f62104e..d7fe720d1b 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
@@ -972,7 +972,8 @@ llvm::TypeSize mlir::LLVM::getPrimitiveTypeSizeInBits(Type type) {
       .Case<IntegerType>([](IntegerType intTy) {
         return llvm::TypeSize::getFixed(intTy.getWidth());
       })
-      .Case<LLVMPPCFP128Type>([](Type) { return llvm::TypeSize::getFixed(128); })
+      .Case<LLVMPPCFP128Type>(
+          [](Type) { return llvm::TypeSize::getFixed(128); })
       .Case<LLVMFixedVectorType>([](LLVMFixedVectorType t) {
         llvm::TypeSize elementSize =
             getPrimitiveTypeSizeInBits(t.getElementType());

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https://github.com/llvm/llvm-project/pull/72994