[Mlir-commits] [mlir] [mlir][ArmSME] Add mask operand to store_tile_slice (PR #70838)

[Cullen Rhodes]

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@@ -518,8 +526,8 @@ def StoreTileSliceOp : ArmSME_Op<"store_tile_slice"> {
   }];
 
   let assemblyFormat = [{
-    $tile `,` $tile_slice_index `,` $base `[` $indices `]` (`layout` `` $layout^)?
-      attr-dict `:` type($base) `,` type($tile)
+    $tile `,` $tile_slice_index `,` $mask `,` $base `[` $indices `]` (`layout` `` $layout^)?
+      attr-dict `:` type($base) `,` type($mask) `,` type($tile)
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c-rhodes wrote:

No it can be inferred as you say, but I decided to add the type anyway since this maps 1-1 with intrinsic. `tile_load`/`tile_store` are aligned with Vector transfer read/write so I didn't add mask type to asm for those.

The type is also present in `load_tile_slice`, we could remove in a follow-up if desired? I've don't mind either way.

https://github.com/llvm/llvm-project/pull/70838