[Mlir-commits] [mlir] a7b50ef - [mlir][openacc] Update acc.data verifier for dataOperands

[Valentin Clement]

Author: Valentin Clement
Date: 2023-05-08T09:27:46-07:00
New Revision: a7b50effcfefc6deb3d061edb7a1a9aaaf851535

URL: https://github.com/llvm/llvm-project/commit/a7b50effcfefc6deb3d061edb7a1a9aaaf851535
DIFF: https://github.com/llvm/llvm-project/commit/a7b50effcfefc6deb3d061edb7a1a9aaaf851535.diff

LOG: [mlir][openacc] Update acc.data verifier for dataOperands

Data operands associated with acc.data should comes
from acc data entry/exit operations or acc.getdeviceptr.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D149992

Added: 
    

Modified: 
    mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
    mlir/test/Dialect/OpenACC/invalid.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
index 35e0ac7632e6c..cb9ed7e0ea44a 100644
--- a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+++ b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
@@ -480,6 +480,15 @@ LogicalResult acc::DataOp::verify() {
   if (getOperands().empty() && !getDefaultAttr())
     return emitError("at least one operand or the default attribute "
                      "must appear on the data operation");
+
+  for (mlir::Value operand : getDataClauseOperands())
+    if (!mlir::isa<acc::AttachOp, acc::CopyinOp, acc::CopyoutOp, acc::CreateOp,
+                   acc::DeleteOp, acc::DetachOp, acc::DevicePtrOp,
+                   acc::GetDevicePtrOp, acc::NoCreateOp, acc::PresentOp>(
+            operand.getDefiningOp()))
+      return emitError("expect data entry/exit operation or acc.getdeviceptr "
+                       "as defining op");
+
   return success();
 }
 

diff  --git a/mlir/test/Dialect/OpenACC/invalid.mlir b/mlir/test/Dialect/OpenACC/invalid.mlir
index 178167ff8d82c..465e0de46fd5d 100644
--- a/mlir/test/Dialect/OpenACC/invalid.mlir
+++ b/mlir/test/Dialect/OpenACC/invalid.mlir
@@ -76,6 +76,14 @@ acc.data {
 
 // -----
 
+%value = memref.alloc() : memref<10xf32>
+// expected-error at +1 {{expect data entry/exit operation or acc.getdeviceptr as defining op}}
+acc.data dataOperands(%value : memref<10xf32>) {
+  acc.yield
+}
+
+// -----
+
 // expected-error at +1 {{at least one value must be present in hostOperands or deviceOperands}}
 acc.update