[Mlir-commits] [mlir] 9170fa5 - [mlir][LLVM] Convert access group metadata to using attributes instead of ops
Markus Böck
llvmlistbot at llvm.org
Fri Jul 14 05:59:45 PDT 2023
Author: Markus Böck
Date: 2023-07-14T14:57:46+02:00
New Revision: 9170fa58082e368f8b6ed8e0e6ef88fad8dd4633
URL: https://github.com/llvm/llvm-project/commit/9170fa58082e368f8b6ed8e0e6ef88fad8dd4633
DIFF: https://github.com/llvm/llvm-project/commit/9170fa58082e368f8b6ed8e0e6ef88fad8dd4633.diff
LOG: [mlir][LLVM] Convert access group metadata to using attributes instead of ops
Using MLIR attributes instead of metadata has many advantages:
* No indirection: Attributes can simply refer to each other seemlessly without having to use the indirection of `SymbolRefAttr`. This also gives us correctness by construction in a lot of places as well
* Multithreading safe: The Attribute infrastructure gives us thread-safety for free. Creating operations and inserting them into a block is not thread-safe. This is a major use case for e.g. the inliner in MLIR which runs in parallel
* Easier to create: There is no need for a builder or a metadata region
This patch therefore does exactly that. It leverages the new distinct attributes to create distinct access groups in a deterministic and threadsafe manner.
Differential Revision: https://reviews.llvm.org/D155285
Added:
Modified:
mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
mlir/include/mlir/Target/LLVMIR/ModuleImport.h
mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h
mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h
mlir/lib/Target/LLVMIR/ModuleImport.cpp
mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
mlir/test/Dialect/LLVMIR/inlining.mlir
mlir/test/Dialect/LLVMIR/invalid.mlir
mlir/test/Dialect/LLVMIR/loop-metadata.mlir
mlir/test/Dialect/LLVMIR/tbaa-invalid.mlir
mlir/test/Target/LLVMIR/Import/metadata-loop.ll
mlir/test/Target/LLVMIR/loop-metadata.mlir
mlir/test/mlir-tblgen/llvm-intrinsics.td
mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
index 56a5682d0bc93f..e2c2ca578558f3 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
@@ -215,7 +215,7 @@ def LoopAnnotationAttr : LLVM_Attr<"LoopAnnotation", "loop_annotation"> {
OptionalParameter<"LoopUnswitchAttr">:$unswitch,
OptionalParameter<"BoolAttr">:$mustProgress,
OptionalParameter<"BoolAttr">:$isVectorized,
- OptionalArrayRefParameter<"SymbolRefAttr">:$parallelAccesses,
+ OptionalArrayRefParameter<"AccessGroupAttr">:$parallelAccesses,
OptionalParameter<"FusedLoc">:$startLoc,
OptionalParameter<"FusedLoc">:$endLoc
);
@@ -650,4 +650,39 @@ def LLVM_AliasScopeArrayAttr
let constBuilderCall = ?;
}
+//===----------------------------------------------------------------------===//
+// AccessGroupAttr
+//===----------------------------------------------------------------------===//
+
+def LLVM_AccessGroupAttr : LLVM_Attr<"AccessGroup", "access_group"> {
+
+ let parameters = (ins "DistinctAttr":$id);
+
+ let builders = [
+ AttrBuilder<(ins), [{
+ return $_get($_ctxt, DistinctAttr::create(UnitAttr::get($_ctxt)));
+ }]>
+ ];
+
+ let summary = "LLVM dialect access group metadata";
+
+ let description = [{
+ Defines an access group metadata that can be set on any instruction
+ that potentially accesses memory via the `AccessGroupOpInterface` or on
+ branch instructions in the loop latch block via the `parallelAccesses`
+ parameter of `LoopAnnotationAttr`.
+
+ See the following link for more details:
+ https://llvm.org/docs/LangRef.html#llvm-access-group-metadata
+ }];
+
+ let assemblyFormat = "`<` struct(params) `>`";
+}
+
+def LLVM_AccessGroupArrayAttr
+ : TypedArrayAttrBase<LLVM_AccessGroupAttr,
+ LLVM_AccessGroupAttr.summary # " array"> {
+ let constBuilderCall = ?;
+}
+
#endif // LLVMIR_ATTRDEFS
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
index 2351da9309842c..7750dca4440a7d 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
@@ -278,7 +278,7 @@ class LLVM_MemAccessOpBase<string mnemonic, list<Trait> traits = []> :
DeclareOpInterfaceMethods<AccessGroupOpInterface>,
DeclareOpInterfaceMethods<AliasAnalysisOpInterface>], traits)>,
LLVM_MemOpPatterns {
- dag aliasAttrs = (ins OptionalAttr<SymbolRefArrayAttr>:$access_groups,
+ dag aliasAttrs = (ins OptionalAttr<LLVM_AccessGroupArrayAttr>:$access_groups,
OptionalAttr<LLVM_AliasScopeArrayAttr>:$alias_scopes,
OptionalAttr<LLVM_AliasScopeArrayAttr>:$noalias_scopes,
OptionalAttr<SymbolRefArrayAttr>:$tbaa);
@@ -321,7 +321,7 @@ class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName,
Results<!if(!gt(numResults, 0), (outs LLVM_Type:$res), (outs))> {
dag aliasAttrs = !con(
!if(!gt(requiresAccessGroup, 0),
- (ins OptionalAttr<SymbolRefArrayAttr>:$access_groups),
+ (ins OptionalAttr<LLVM_AccessGroupArrayAttr>:$access_groups),
(ins )),
!if(!gt(requiresAliasAnalysis, 0),
(ins OptionalAttr<LLVM_AliasScopeArrayAttr>:$alias_scopes,
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
index 81374930bd5386..04389f0efdfbae 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
@@ -845,7 +845,6 @@ def LLVM_BrOp : LLVM_TerminatorOp<"br",
}]>,
LLVM_TerminatorPassthroughOpBuilder
];
- let hasVerifier = 1;
}
def LLVM_CondBrOp : LLVM_TerminatorOp<"cond_br",
[AttrSizedOperandSegments, DeclareOpInterfaceMethods<BranchOpInterface>,
@@ -880,7 +879,6 @@ def LLVM_CondBrOp : LLVM_TerminatorOp<"cond_br",
build($_builder, $_state, condition, trueOperands, falseOperands, branchWeights,
{}, trueDest, falseDest);
}]>, LLVM_TerminatorPassthroughOpBuilder];
- let hasVerifier = 1;
}
//===----------------------------------------------------------------------===//
@@ -1101,26 +1099,6 @@ def LLVM_MetadataOp : LLVM_Op<"metadata", [
let hasRegionVerifier = 1;
}
-def LLVM_AccessGroupMetadataOp : LLVM_Op<"access_group", [
- HasParent<"MetadataOp">, Symbol
-]> {
- let arguments = (ins
- SymbolNameAttr:$sym_name
- );
- let summary = "LLVM dialect access group metadata.";
- let description = [{
- Defines an access group metadata that can be attached to any instruction
- that potentially accesses memory. The access group may be attached to a
- memory accessing instruction via the `llvm.access.group` metadata and
- a branch instruction in the loop latch block via the
- `llvm.loop.parallel_accesses` metadata.
-
- See the following link for more details:
- https://llvm.org/docs/LangRef.html#llvm-access-group-metadata
- }];
- let assemblyFormat = "$sym_name attr-dict";
-}
-
def LLVM_TBAARootMetadataOp : LLVM_Op<"tbaa_root", [
HasParent<"MetadataOp">, Symbol
]> {
diff --git a/mlir/include/mlir/Target/LLVMIR/ModuleImport.h b/mlir/include/mlir/Target/LLVMIR/ModuleImport.h
index 14263889d5cb1d..d86c95ad8e3e76 100644
--- a/mlir/include/mlir/Target/LLVMIR/ModuleImport.h
+++ b/mlir/include/mlir/Target/LLVMIR/ModuleImport.h
@@ -191,10 +191,10 @@ class ModuleImport {
return tbaaMapping.lookup(node);
}
- /// Returns the symbol references pointing to the access group operations that
- /// map to the access group nodes starting from the access group metadata
- /// `node`. Returns failure, if any of the symbol references cannot be found.
- FailureOr<SmallVector<SymbolRefAttr>>
+ /// Returns the access group attributes that map to the access group nodes
+ /// starting from the access group metadata `node`. Returns failure, if any of
+ /// the attributes cannot be found.
+ FailureOr<SmallVector<AccessGroupAttr>>
lookupAccessGroupAttrs(const llvm::MDNode *node) const;
/// Returns the loop annotation attribute that corresponds to the given LLVM
diff --git a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
index f8e621009317b0..8f3fcc5284dc2f 100644
--- a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
+++ b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
@@ -278,10 +278,6 @@ class ModuleTranslation {
LogicalResult convertGlobals();
LogicalResult convertOneFunction(LLVMFuncOp func);
- /// Process access_group LLVM Metadata operations and create LLVM
- /// metadata nodes.
- LogicalResult createAccessGroupMetadata();
-
/// Process alias.scope LLVM Metadata operations and create LLVM
/// metadata nodes for them and their domains.
LogicalResult createAliasScopeMetadata();
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index b0369094e6ecf2..f06810968d6844 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -291,42 +291,11 @@ Type AllocaOp::getResultPtrElementType() {
// LLVM::BrOp
//===----------------------------------------------------------------------===//
-/// Check if the `loopAttr` references correct symbols.
-static LogicalResult verifyLoopAnnotationAttr(LoopAnnotationAttr loopAttr,
- Operation *op) {
- if (!loopAttr)
- return success();
- // If the `llvm.loop` attribute is present, enforce the following structure,
- // which the module translation can assume.
- ArrayRef<SymbolRefAttr> parallelAccesses = loopAttr.getParallelAccesses();
- if (parallelAccesses.empty())
- return success();
- for (SymbolRefAttr accessGroupRef : parallelAccesses) {
- StringAttr metadataName = accessGroupRef.getRootReference();
- auto metadataOp = SymbolTable::lookupNearestSymbolFrom<LLVM::MetadataOp>(
- op->getParentOp(), metadataName);
- if (!metadataOp)
- return op->emitOpError() << "expected '" << accessGroupRef
- << "' to reference a metadata op";
- StringAttr accessGroupName = accessGroupRef.getLeafReference();
- Operation *accessGroupOp =
- SymbolTable::lookupNearestSymbolFrom(metadataOp, accessGroupName);
- if (!accessGroupOp)
- return op->emitOpError() << "expected '" << accessGroupRef
- << "' to reference an access_group op";
- }
- return success();
-}
-
SuccessorOperands BrOp::getSuccessorOperands(unsigned index) {
assert(index == 0 && "invalid successor index");
return SuccessorOperands(getDestOperandsMutable());
}
-LogicalResult BrOp::verify() {
- return verifyLoopAnnotationAttr(getLoopAnnotationAttr(), *this);
-}
-
//===----------------------------------------------------------------------===//
// LLVM::CondBrOp
//===----------------------------------------------------------------------===//
@@ -337,10 +306,6 @@ SuccessorOperands CondBrOp::getSuccessorOperands(unsigned index) {
: getFalseDestOperandsMutable());
}
-LogicalResult CondBrOp::verify() {
- return verifyLoopAnnotationAttr(getLoopAnnotationAttr(), *this);
-}
-
void CondBrOp::build(OpBuilder &builder, OperationState &result,
Value condition, Block *trueDest, ValueRange trueOperands,
Block *falseDest, ValueRange falseOperands,
@@ -3094,9 +3059,9 @@ struct LLVMOpAsmDialectInterface : public OpAsmDialectInterface {
AliasResult getAlias(Attribute attr, raw_ostream &os) const override {
return TypeSwitch<Attribute, AliasResult>(attr)
- .Case<AliasScopeAttr, AliasScopeDomainAttr, DIBasicTypeAttr,
- DICompileUnitAttr, DICompositeTypeAttr, DIDerivedTypeAttr,
- DIFileAttr, DILabelAttr, DILexicalBlockAttr,
+ .Case<AccessGroupAttr, AliasScopeAttr, AliasScopeDomainAttr,
+ DIBasicTypeAttr, DICompileUnitAttr, DICompositeTypeAttr,
+ DIDerivedTypeAttr, DIFileAttr, DILabelAttr, DILexicalBlockAttr,
DILexicalBlockFileAttr, DILocalVariableAttr, DINamespaceAttr,
DINullTypeAttr, DISubprogramAttr, DISubroutineTypeAttr,
LoopAnnotationAttr, LoopVectorizeAttr, LoopInterleaveAttr,
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
index 6f70e4e4069295..ff6f4287589a3d 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
@@ -87,9 +87,13 @@ LogicalResult verifySymbolRefsPointTo(Operation *op, StringRef name,
LogicalResult mlir::LLVM::detail::verifyAccessGroupOpInterface(Operation *op) {
auto iface = cast<AccessGroupOpInterface>(op);
- if (failed(verifySymbolRefsPointTo<LLVM::AccessGroupMetadataOp>(
- iface, "access groups", iface.getAccessGroupsOrNull())))
- return failure();
+ ArrayAttr accessGroups = iface.getAccessGroupsOrNull();
+ if (!accessGroups)
+ return success();
+ for (Attribute iter : accessGroups)
+ if (!isa<AccessGroupAttr>(iter))
+ return op->emitOpError("expected op to return array of ")
+ << AccessGroupAttr::getMnemonic() << " attributes";
return success();
}
diff --git a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
index f59dd7616103dd..aa67ba78763455 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
@@ -158,7 +158,7 @@ static LogicalResult setTBAAAttr(const llvm::MDNode *node, Operation *op,
static LogicalResult setAccessGroupsAttr(const llvm::MDNode *node,
Operation *op,
LLVM::ModuleImport &moduleImport) {
- FailureOr<SmallVector<SymbolRefAttr>> accessGroups =
+ FailureOr<SmallVector<AccessGroupAttr>> accessGroups =
moduleImport.lookupAccessGroupAttrs(node);
if (failed(accessGroups))
return failure();
@@ -168,8 +168,7 @@ static LogicalResult setAccessGroupsAttr(const llvm::MDNode *node,
return failure();
iface.setAccessGroups(ArrayAttr::get(
- iface.getContext(),
- SmallVector<Attribute>{accessGroups->begin(), accessGroups->end()}));
+ iface.getContext(), llvm::to_vector_of<Attribute>(*accessGroups)));
return success();
}
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
index a9f080ef0044ff..8dc53a4326ed44 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
@@ -53,7 +53,7 @@ struct LoopMetadataConversion {
FailureOr<LoopPipelineAttr> convertPipelineAttr();
FailureOr<LoopPeeledAttr> convertPeeledAttr();
FailureOr<LoopUnswitchAttr> convertUnswitchAttr();
- FailureOr<SmallVector<SymbolRefAttr>> convertParallelAccesses();
+ FailureOr<SmallVector<AccessGroupAttr>> convertParallelAccesses();
FusedLoc convertStartLoc();
FailureOr<FusedLoc> convertEndLoc();
@@ -391,15 +391,15 @@ FailureOr<LoopUnswitchAttr> LoopMetadataConversion::convertUnswitchAttr() {
return createIfNonNull<LoopUnswitchAttr>(ctx, partialDisable);
}
-FailureOr<SmallVector<SymbolRefAttr>>
+FailureOr<SmallVector<AccessGroupAttr>>
LoopMetadataConversion::convertParallelAccesses() {
FailureOr<SmallVector<llvm::MDNode *>> nodes =
lookupMDNodes("llvm.loop.parallel_accesses");
if (failed(nodes))
return failure();
- SmallVector<SymbolRefAttr> refs;
+ SmallVector<AccessGroupAttr> refs;
for (llvm::MDNode *node : *nodes) {
- FailureOr<SmallVector<SymbolRefAttr>> accessGroups =
+ FailureOr<SmallVector<AccessGroupAttr>> accessGroups =
loopAnnotationImporter.lookupAccessGroupAttrs(node);
if (failed(accessGroups)) {
emitWarning(loc) << "could not lookup access group";
@@ -445,7 +445,7 @@ LoopAnnotationAttr LoopMetadataConversion::convert() {
FailureOr<BoolAttr> mustProgress = lookupUnitNode("llvm.loop.mustprogress");
FailureOr<BoolAttr> isVectorized =
lookupIntNodeAsBoolAttr("llvm.loop.isvectorized");
- FailureOr<SmallVector<SymbolRefAttr>> parallelAccesses =
+ FailureOr<SmallVector<AccessGroupAttr>> parallelAccesses =
convertParallelAccesses();
// Drop the metadata if there are parts that cannot be imported.
@@ -483,8 +483,9 @@ LoopAnnotationImporter::translateLoopAnnotation(const llvm::MDNode *node,
return attr;
}
-LogicalResult LoopAnnotationImporter::translateAccessGroup(
- const llvm::MDNode *node, Location loc, MetadataOp metadataOp) {
+LogicalResult
+LoopAnnotationImporter::translateAccessGroup(const llvm::MDNode *node,
+ Location loc) {
SmallVector<const llvm::MDNode *> accessGroups;
if (!node->getNumOperands())
accessGroups.push_back(node);
@@ -504,24 +505,17 @@ LogicalResult LoopAnnotationImporter::translateAccessGroup(
return emitWarning(loc)
<< "expected an access group node to be empty and distinct";
- OpBuilder::InsertionGuard guard(builder);
- builder.setInsertionPointToEnd(&metadataOp.getBody().back());
- auto groupOp = builder.create<AccessGroupMetadataOp>(
- loc, llvm::formatv("group_{0}", accessGroupMapping.size()).str());
- // Add a mapping from the access group node to the symbol reference pointing
- // to the newly created operation.
- accessGroupMapping[accessGroup] = SymbolRefAttr::get(
- builder.getContext(), metadataOp.getSymName(),
- FlatSymbolRefAttr::get(builder.getContext(), groupOp.getSymName()));
+ // Add a mapping from the access group node to the newly created attribute.
+ accessGroupMapping[accessGroup] = builder.getAttr<AccessGroupAttr>();
}
return success();
}
-FailureOr<SmallVector<SymbolRefAttr>>
+FailureOr<SmallVector<AccessGroupAttr>>
LoopAnnotationImporter::lookupAccessGroupAttrs(const llvm::MDNode *node) const {
// An access group node is either a single access group or an access group
// list.
- SmallVector<SymbolRefAttr> accessGroups;
+ SmallVector<AccessGroupAttr> accessGroups;
if (!node->getNumOperands())
accessGroups.push_back(accessGroupMapping.lookup(node));
for (const llvm::MDOperand &operand : node->operands()) {
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h
index 7dcfc4c750d98a..d5a5f70b46e2e1 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h
@@ -32,17 +32,15 @@ class LoopAnnotationImporter {
Location loc);
/// Converts all LLVM access groups starting from node to MLIR access group
- /// operations mested in the region of metadataOp. It stores a mapping from
- /// every nested access group nod to the symbol pointing to the translated
- /// operation. Returns success if all conversions succeed and failure
- /// otherwise.
- LogicalResult translateAccessGroup(const llvm::MDNode *node, Location loc,
- MetadataOp metadataOp);
+ /// attributes. It stores a mapping from every nested access group node to the
+ /// translated attribute. Returns success if all conversions succeed and
+ /// failure otherwise.
+ LogicalResult translateAccessGroup(const llvm::MDNode *node, Location loc);
- /// Returns the symbol references pointing to the access group operations that
- /// map to the access group nodes starting from the access group metadata
- /// node. Returns failure, if any of the symbol references cannot be found.
- FailureOr<SmallVector<SymbolRefAttr>>
+ /// Returns the access group attribute that map to the access group nodes
+ /// starting from the access group metadata node. Returns failure, if any of
+ /// the attributes cannot be found.
+ FailureOr<SmallVector<AccessGroupAttr>>
lookupAccessGroupAttrs(const llvm::MDNode *node) const;
/// The ModuleImport owning this instance.
@@ -63,9 +61,9 @@ class LoopAnnotationImporter {
OpBuilder &builder;
DenseMap<const llvm::MDNode *, LoopAnnotationAttr> loopMetadataMapping;
- /// Mapping between original LLVM access group metadata nodes and the symbol
- /// references pointing to the imported MLIR access group operations.
- DenseMap<const llvm::MDNode *, SymbolRefAttr> accessGroupMapping;
+ /// Mapping between original LLVM access group metadata nodes and the imported
+ /// MLIR access group attributes.
+ DenseMap<const llvm::MDNode *, AccessGroupAttr> accessGroupMapping;
};
} // namespace detail
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
index fbbfa1fcdf1d1a..1dde457b5c34ff 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
@@ -240,14 +240,14 @@ llvm::MDNode *LoopAnnotationConversion::convert() {
if (auto options = attr.getUnswitch())
convertLoopOptions(options);
- ArrayRef<SymbolRefAttr> parallelAccessGroups = attr.getParallelAccesses();
+ ArrayRef<AccessGroupAttr> parallelAccessGroups = attr.getParallelAccesses();
if (!parallelAccessGroups.empty()) {
SmallVector<llvm::Metadata *> parallelAccess;
parallelAccess.push_back(
llvm::MDString::get(ctx, "llvm.loop.parallel_accesses"));
- for (SymbolRefAttr accessGroupRef : parallelAccessGroups)
+ for (AccessGroupAttr accessGroupAttr : parallelAccessGroups)
parallelAccess.push_back(
- loopAnnotationTranslation.getAccessGroup(op, accessGroupRef));
+ loopAnnotationTranslation.getAccessGroup(accessGroupAttr));
metadataNodes.push_back(llvm::MDNode::get(ctx, parallelAccess));
}
@@ -277,38 +277,24 @@ LoopAnnotationTranslation::translateLoopAnnotation(LoopAnnotationAttr attr,
return loopMD;
}
-LogicalResult LoopAnnotationTranslation::createAccessGroupMetadata() {
- mlirModule->walk([&](LLVM::MetadataOp metadatas) {
- metadatas.walk([&](LLVM::AccessGroupMetadataOp op) {
- llvm::MDNode *accessGroup =
- llvm::MDNode::getDistinct(llvmModule.getContext(), {});
- accessGroupMetadataMapping.insert({op, accessGroup});
- });
- });
- return success();
-}
-
llvm::MDNode *
-LoopAnnotationTranslation::getAccessGroup(Operation *op,
- SymbolRefAttr accessGroupRef) const {
- auto metadataName = accessGroupRef.getRootReference();
- auto accessGroupName = accessGroupRef.getLeafReference();
- auto metadataOp = SymbolTable::lookupNearestSymbolFrom<LLVM::MetadataOp>(
- op->getParentOp(), metadataName);
- auto *accessGroupOp =
- SymbolTable::lookupNearestSymbolFrom(metadataOp, accessGroupName);
- return accessGroupMetadataMapping.lookup(accessGroupOp);
+LoopAnnotationTranslation::getAccessGroup(AccessGroupAttr accessGroupAttr) {
+ auto [result, inserted] =
+ accessGroupMetadataMapping.insert({accessGroupAttr, nullptr});
+ if (inserted)
+ result->second = llvm::MDNode::getDistinct(llvmModule.getContext(), {});
+ return result->second;
}
llvm::MDNode *
-LoopAnnotationTranslation::getAccessGroups(AccessGroupOpInterface op) const {
- ArrayAttr accessGroupRefs = op.getAccessGroupsOrNull();
- if (!accessGroupRefs || accessGroupRefs.empty())
+LoopAnnotationTranslation::getAccessGroups(AccessGroupOpInterface op) {
+ ArrayAttr accessGroups = op.getAccessGroupsOrNull();
+ if (!accessGroups || accessGroups.empty())
return nullptr;
SmallVector<llvm::Metadata *> groupMDs;
- for (SymbolRefAttr groupRef : accessGroupRefs.getAsRange<SymbolRefAttr>())
- groupMDs.push_back(getAccessGroup(op, groupRef));
+ for (AccessGroupAttr group : accessGroups.getAsRange<AccessGroupAttr>())
+ groupMDs.push_back(getAccessGroup(group));
if (groupMDs.size() == 1)
return llvm::cast<llvm::MDNode>(groupMDs.front());
return llvm::MDNode::get(llvmModule.getContext(), groupMDs);
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h
index 0e016d9cbeef0b..32d3c39e1f424f 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h
@@ -26,24 +26,18 @@ namespace detail {
class LoopAnnotationTranslation {
public:
LoopAnnotationTranslation(ModuleTranslation &moduleTranslation,
- Operation *mlirModule, llvm::Module &llvmModule)
- : moduleTranslation(moduleTranslation), mlirModule(mlirModule),
- llvmModule(llvmModule) {}
+ llvm::Module &llvmModule)
+ : moduleTranslation(moduleTranslation), llvmModule(llvmModule) {}
llvm::MDNode *translateLoopAnnotation(LoopAnnotationAttr attr, Operation *op);
- /// Traverses the global access group metadata operation in the `mlirModule`
- /// and creates corresponding LLVM metadata nodes.
- LogicalResult createAccessGroupMetadata();
+ /// Returns the LLVM metadata corresponding to an mlir LLVM dialect access
+ /// group attribute.
+ llvm::MDNode *getAccessGroup(AccessGroupAttr accessGroupAttr);
- /// Returns the LLVM metadata corresponding to a symbol reference to an mlir
- /// LLVM dialect access group operation.
- llvm::MDNode *getAccessGroup(Operation *op,
- SymbolRefAttr accessGroupRef) const;
-
- /// Returns the LLVM metadata corresponding to the access group operations
+ /// Returns the LLVM metadata corresponding to the access group attribute
/// referenced by the AccessGroupOpInterface or null if there are none.
- llvm::MDNode *getAccessGroups(AccessGroupOpInterface op) const;
+ llvm::MDNode *getAccessGroups(AccessGroupOpInterface op);
/// The ModuleTranslation owning this instance.
ModuleTranslation &moduleTranslation;
@@ -65,12 +59,11 @@ class LoopAnnotationTranslation {
/// The metadata is attached to Latch block branches with this attribute.
DenseMap<Attribute, llvm::MDNode *> loopMetadataMapping;
- /// Mapping from an access group metadata operation to its LLVM metadata.
+ /// Mapping from an access group attribute to its LLVM metadata.
/// This map is populated on module entry and is used to annotate loops (as
/// identified via their branches) and contained memory accesses.
- DenseMap<Operation *, llvm::MDNode *> accessGroupMetadataMapping;
+ DenseMap<AccessGroupAttr, llvm::MDNode *> accessGroupMetadataMapping;
- Operation *mlirModule;
llvm::Module &llvmModule;
};
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index e47af5acba0aaa..3119aac6161892 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -434,8 +434,7 @@ LogicalResult ModuleImport::processTBAAMetadata(const llvm::MDNode *node) {
LogicalResult
ModuleImport::processAccessGroupMetadata(const llvm::MDNode *node) {
Location loc = mlirModule.getLoc();
- if (failed(loopAnnotationImporter->translateAccessGroup(
- node, loc, getGlobalMetadataOp())))
+ if (failed(loopAnnotationImporter->translateAccessGroup(node, loc)))
return emitError(loc) << "unsupported access group node: "
<< diagMD(node, llvmModule.get());
return success();
@@ -1803,7 +1802,7 @@ LogicalResult ModuleImport::processBasicBlock(llvm::BasicBlock *bb,
return success();
}
-FailureOr<SmallVector<SymbolRefAttr>>
+FailureOr<SmallVector<AccessGroupAttr>>
ModuleImport::lookupAccessGroupAttrs(const llvm::MDNode *node) const {
return loopAnnotationImporter->lookupAccessGroupAttrs(node);
}
diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
index 7b18388a44627d..a767f30c9b50d8 100644
--- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
@@ -462,7 +462,7 @@ ModuleTranslation::ModuleTranslation(Operation *module,
debugTranslation(
std::make_unique<DebugTranslation>(module, *this->llvmModule)),
loopAnnotationTranslation(std::make_unique<LoopAnnotationTranslation>(
- *this, module, *this->llvmModule)),
+ *this, *this->llvmModule)),
typeTranslator(this->llvmModule->getContext()),
iface(module->getContext()) {
assert(satisfiesLLVMModule(mlirModule) &&
@@ -1083,10 +1083,6 @@ LogicalResult ModuleTranslation::convertComdats() {
return success();
}
-LogicalResult ModuleTranslation::createAccessGroupMetadata() {
- return loopAnnotationTranslation->createAccessGroupMetadata();
-}
-
void ModuleTranslation::setAccessGroupsMetadata(AccessGroupOpInterface op,
llvm::Instruction *inst) {
if (llvm::MDNode *node = loopAnnotationTranslation->getAccessGroups(op))
@@ -1419,8 +1415,6 @@ mlir::translateModuleToLLVMIR(Operation *module, llvm::LLVMContext &llvmContext,
return nullptr;
if (failed(translator.convertGlobals()))
return nullptr;
- if (failed(translator.createAccessGroupMetadata()))
- return nullptr;
if (failed(translator.createAliasScopeMetadata()))
return nullptr;
if (failed(translator.createTBAAMetadata()))
diff --git a/mlir/test/Dialect/LLVMIR/inlining.mlir b/mlir/test/Dialect/LLVMIR/inlining.mlir
index cf438f93d74d20..7ad92ad0e04d72 100644
--- a/mlir/test/Dialect/LLVMIR/inlining.mlir
+++ b/mlir/test/Dialect/LLVMIR/inlining.mlir
@@ -54,13 +54,10 @@ func.func @test_inline(%ptr : !llvm.ptr) -> i32 {
// -----
-llvm.metadata @metadata {
- llvm.access_group @group
- llvm.return
-}
+#group = #llvm.access_group<id = distinct[0]<>>
llvm.func @inlinee(%ptr : !llvm.ptr) -> i32 {
- %0 = llvm.load %ptr { access_groups = [@metadata::@group] } : !llvm.ptr -> i32
+ %0 = llvm.load %ptr { access_groups = [#group] } : !llvm.ptr -> i32
llvm.return %0 : i32
}
@@ -73,16 +70,13 @@ llvm.func @test_not_inline(%ptr : !llvm.ptr) -> i32 {
// -----
-llvm.metadata @metadata {
- llvm.access_group @group
- llvm.return
-}
+#group = #llvm.access_group<id = distinct[0]<>>
func.func private @with_mem_attr(%ptr : !llvm.ptr) {
%0 = llvm.mlir.constant(42 : i32) : i32
// Do not inline load/store operations that carry attributes requiring
// handling while inlining, until this is supported by the inliner.
- llvm.store %0, %ptr { access_groups = [@metadata::@group] }: i32, !llvm.ptr
+ llvm.store %0, %ptr { access_groups = [#group] }: i32, !llvm.ptr
return
}
diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir
index d1c6849c6ce3e5..da4799d8a26392 100644
--- a/mlir/test/Dialect/LLVMIR/invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/invalid.mlir
@@ -911,36 +911,9 @@ llvm.mlir.global appending @non_array_type_global_appending_linkage() : i32
// -----
-module {
- llvm.func @loopOptions() {
- // expected-error at below {{expected '@func1' to reference a metadata op}}
- llvm.br ^bb4 {loop_annotation = #llvm.loop_annotation<parallelAccesses = @func1>}
- ^bb4:
- llvm.return
- }
- llvm.func @func1() {
- llvm.return
- }
-}
-
-// -----
-
-module {
- llvm.func @loopOptions() {
- // expected-error at below {{expected '@metadata' to reference an access_group op}}
- llvm.br ^bb4 {loop_annotation = #llvm.loop_annotation<parallelAccesses = @metadata>}
- ^bb4:
- llvm.return
- }
- llvm.metadata @metadata {
- }
-}
-
-// -----
-
module {
llvm.func @accessGroups(%arg0 : !llvm.ptr) {
- // expected-error at below {{expected '@func1' to specify a fully qualified reference}}
+ // expected-error at below {{attribute 'access_groups' failed to satisfy constraint: LLVM dialect access group metadata array}}
%0 = llvm.load %arg0 { "access_groups" = [@func1] } : !llvm.ptr -> i32
llvm.return
}
@@ -951,33 +924,9 @@ module {
// -----
-module {
- llvm.func @accessGroups(%arg0 : i32, %arg1 : !llvm.ptr) {
- // expected-error at below {{expected '@accessGroups::@group1' to reference a metadata op}}
- llvm.store %arg0, %arg1 { "access_groups" = [@accessGroups::@group1] } : i32, !llvm.ptr
- llvm.return
- }
- llvm.metadata @metadata {
- }
-}
-
-// -----
-
-module {
- llvm.func @accessGroups(%arg0 : !llvm.ptr, %arg1 : f32) {
- // expected-error at below {{expected '@metadata::@group1' to be a valid reference}}
- %0 = llvm.atomicrmw fadd %arg0, %arg1 monotonic { "access_groups" = [@metadata::@group1] } : !llvm.ptr, f32
- llvm.return
- }
- llvm.metadata @metadata {
- }
-}
-
-// -----
-
module {
llvm.func @accessGroups(%arg0 : !llvm.ptr, %arg1 : i32, %arg2 : i32) {
- // expected-error at below {{expected '@metadata::@scope' to resolve to a llvm.access_group}}
+ // expected-error at below {{attribute 'access_groups' failed to satisfy constraint: LLVM dialect access group metadata array}}
%0 = llvm.cmpxchg %arg0, %arg1, %arg2 acq_rel monotonic { "access_groups" = [@metadata::@scope] } : !llvm.ptr, i32
llvm.return
}
diff --git a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
index 631f27139ba9fe..bae20d1d6818ee 100644
--- a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
@@ -42,6 +42,11 @@
// CHECK-DAG: #[[UNSWITCH:.*]] = #llvm.loop_unswitch<partialDisable = true>
#unswitch = #llvm.loop_unswitch<partialDisable = true>
+// CHECK-DAG: #[[GROUP1:.*]] = #llvm.access_group<id = {{.*}}>
+// CHECK-DAG: #[[GROUP2:.*]] = #llvm.access_group<id = {{.*}}>
+#group1 = #llvm.access_group<id = distinct[0]<>>
+#group2 = #llvm.access_group<id = distinct[1]<>>
+
// CHECK: #[[LOOP_ANNOT:.*]] = #llvm.loop_annotation<
// CHECK-DAG: disableNonforced = false
// CHECK-DAG: mustProgress = true
@@ -53,7 +58,7 @@
// CHECK-DAG: peeled = #[[PEELED]]
// CHECK-DAG: unswitch = #[[UNSWITCH]]
// CHECK-DAG: isVectorized = false
-// CHECK-DAG: parallelAccesses = @metadata::@group1, @metadata::@group2>
+// CHECK-DAG: parallelAccesses = #[[GROUP1]], #[[GROUP2]]>
#loopMD = #llvm.loop_annotation<disableNonforced = false,
mustProgress = true,
vectorize = #vectorize,
@@ -66,7 +71,7 @@
peeled = #peeled,
unswitch = #unswitch,
isVectorized = false,
- parallelAccesses = @metadata::@group1, @metadata::@group2>
+ parallelAccesses = #group1, #group2>
// CHECK: llvm.func @loop_annotation
llvm.func @loop_annotation() {
@@ -76,11 +81,6 @@ llvm.func @loop_annotation() {
llvm.return
}
-llvm.metadata @metadata {
- llvm.access_group @group1
- llvm.access_group @group2
-}
-
// -----
#di_file = #llvm.di_file<"metadata-loop.ll" in "/">
diff --git a/mlir/test/Dialect/LLVMIR/tbaa-invalid.mlir b/mlir/test/Dialect/LLVMIR/tbaa-invalid.mlir
index a747d596bd968c..8924c9f0410d3a 100644
--- a/mlir/test/Dialect/LLVMIR/tbaa-invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/tbaa-invalid.mlir
@@ -32,7 +32,7 @@ module {
llvm.return
}
llvm.metadata @metadata {
- llvm.access_group @group1
+ llvm.func @group1()
}
}
diff --git a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
index 9638ebd0dc1973..3516101a2367de 100644
--- a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
+++ b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
@@ -1,19 +1,17 @@
; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK: llvm.access_group @[[$GROUP0:.*]]
-; CHECK: llvm.access_group @[[$GROUP1:.*]]
-; CHECK: llvm.access_group @[[$GROUP2:.*]]
-; CHECK: llvm.access_group @[[$GROUP3:.*]]
-; CHECK: }
+; CHECK-DAG: #[[$GROUP0:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK-DAG: #[[$GROUP1:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK-DAG: #[[$GROUP2:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK-DAG: #[[$GROUP3:.*]] = #llvm.access_group<id = {{.*}}>
; CHECK-LABEL: llvm.func @access_group
define void @access_group(ptr %arg1) {
- ; CHECK: access_groups = [@__llvm_global_metadata::@[[$GROUP0]], @__llvm_global_metadata::@[[$GROUP1]]]
+ ; CHECK: access_groups = [#[[$GROUP0]], #[[$GROUP1]]]
%1 = load i32, ptr %arg1, !llvm.access.group !0
- ; CHECK: access_groups = [@__llvm_global_metadata::@[[$GROUP2]], @__llvm_global_metadata::@[[$GROUP0]]]
+ ; CHECK: access_groups = [#[[$GROUP2]], #[[$GROUP0]]]
%2 = load i32, ptr %arg1, !llvm.access.group !1
- ; CHECK: access_groups = [@__llvm_global_metadata::@[[$GROUP3]]]
+ ; CHECK: access_groups = [#[[$GROUP3]]]
%3 = load i32, ptr %arg1, !llvm.access.group !2
ret void
}
@@ -284,10 +282,8 @@ end:
; // -----
-; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = @__llvm_global_metadata::@[[GROUP0:.*]]>
-
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK: llvm.access_group @[[GROUP0]]
+; CHECK: #[[GROUP0:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = #[[GROUP0]]>
; CHECK-LABEL: @parallel_accesses
define void @parallel_accesses(ptr %arg) {
@@ -305,11 +301,9 @@ end:
; // -----
-; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = @__llvm_global_metadata::@[[GROUP0:.*]], @__llvm_global_metadata::@[[GROUP1:.*]]>
-
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK: llvm.access_group @[[GROUP0]]
-; CHECK: llvm.access_group @[[GROUP1]]
+; CHECK: #[[GROUP0:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK: #[[GROUP1:.*]] = #llvm.access_group<id = {{.*}}>
+; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = #[[GROUP0]], #[[GROUP1]]>
; CHECK-LABEL: @multiple_parallel_accesses
define void @multiple_parallel_accesses(ptr %arg) {
@@ -330,8 +324,7 @@ end:
; // -----
; Verify the unused access group is not imported.
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK-COUNT1: llvm.access_group
+; CHECK-COUNT1: #llvm.access_group
; CHECK-LABEL: @unused_parallel_access
define void @unused_parallel_access(ptr %arg) {
diff --git a/mlir/test/Target/LLVMIR/loop-metadata.mlir b/mlir/test/Target/LLVMIR/loop-metadata.mlir
index f889388ab97e1b..a9aeebfa4d82d0 100644
--- a/mlir/test/Target/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Target/LLVMIR/loop-metadata.mlir
@@ -235,6 +235,9 @@ llvm.func @unswitchOptions() {
llvm.func @foo(%arg0: i32)
+#group1 = #llvm.access_group<id = distinct[0]<>>
+#group2 = #llvm.access_group<id = distinct[1]<>>
+
// CHECK-LABEL: @loopOptions
llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) {
%0 = llvm.mlir.constant(0 : i32) : i32
@@ -247,40 +250,35 @@ llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) {
licm = <disable = true>,
interleave = <count = 1>,
unroll = <disable = true>, pipeline = <disable = true, initiationinterval = 2>,
- parallelAccesses = @metadata::@group1, @metadata::@group2>}
+ parallelAccesses = #group1, #group2>}
^bb4:
%3 = llvm.add %1, %arg2 : i32
// CHECK: = load i32, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE:[0-9]+]]
- %5 = llvm.load %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr -> i32
+ %5 = llvm.load %4 {access_groups = [#group1, #group2]} : !llvm.ptr -> i32
// CHECK: store i32 %{{.*}}, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- llvm.store %5, %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : i32, !llvm.ptr
+ llvm.store %5, %4 {access_groups = [#group1, #group2]} : i32, !llvm.ptr
// CHECK: = atomicrmw add ptr %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- %6 = llvm.atomicrmw add %4, %5 monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
+ %6 = llvm.atomicrmw add %4, %5 monotonic {access_groups = [#group1, #group2]} : !llvm.ptr, i32
// CHECK: = cmpxchg ptr %{{.*}}, i32 %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- %7 = llvm.cmpxchg %4, %5, %6 acq_rel monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
+ %7 = llvm.cmpxchg %4, %5, %6 acq_rel monotonic {access_groups = [#group1, #group2]} : !llvm.ptr, i32
%9 = llvm.mlir.constant(42 : i8) : i8
// CHECK: llvm.memcpy{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- "llvm.intr.memcpy"(%4, %4, %0) <{isVolatile = false}> {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, !llvm.ptr, i32) -> ()
+ "llvm.intr.memcpy"(%4, %4, %0) <{isVolatile = false}> {access_groups = [#group1, #group2]} : (!llvm.ptr, !llvm.ptr, i32) -> ()
// CHECK: llvm.memset{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- "llvm.intr.memset"(%4, %9, %0) <{isVolatile = false}> {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, i8, i32) -> ()
+ "llvm.intr.memset"(%4, %9, %0) <{isVolatile = false}> {access_groups = [#group1, #group2]} : (!llvm.ptr, i8, i32) -> ()
// CHECK: call void @foo({{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
- llvm.call @foo(%arg1) {access_groups = [@metadata::@group1, @metadata::@group2]} : (i32) -> ()
+ llvm.call @foo(%arg1) {access_groups = [#group1, #group2]} : (i32) -> ()
// CHECK: br label {{.*}} !llvm.loop ![[LOOP_NODE]]
llvm.br ^bb3(%3 : i32) {loop_annotation = #llvm.loop_annotation<
licm = <disable = true>,
interleave = <count = 1>,
unroll = <disable = true>, pipeline = <disable = true, initiationinterval = 2>,
- parallelAccesses = @metadata::@group1, @metadata::@group2>}
+ parallelAccesses = #group1, #group2>}
^bb5:
llvm.return
}
-llvm.metadata @metadata {
- llvm.access_group @group1
- llvm.access_group @group2
-}
-
// CHECK: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}}
// CHECK-DAG: ![[PA_NODE:[0-9]+]] = !{!"llvm.loop.parallel_accesses", ![[GROUP_NODE1:[0-9]+]], ![[GROUP_NODE2:[0-9]+]]}
// CHECK-DAG: ![[GROUP_NODE1:[0-9]+]] = distinct !{}
diff --git a/mlir/test/mlir-tblgen/llvm-intrinsics.td b/mlir/test/mlir-tblgen/llvm-intrinsics.td
index 2594674564df16..6c2ef4eb811e7b 100644
--- a/mlir/test/mlir-tblgen/llvm-intrinsics.td
+++ b/mlir/test/mlir-tblgen/llvm-intrinsics.td
@@ -50,7 +50,7 @@
// It does not implement the alias analysis interface.
// GROUPS: 0>
// It has an access group attribute.
-// GROUPS: OptionalAttr<SymbolRefArrayAttr>:$access_groups
+// GROUPS: OptionalAttr<LLVM_AccessGroupArrayAttr>:$access_groups
//---------------------------------------------------------------------------//
diff --git a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
index fef08cd8f3d114..f9b4031f22cece 100644
--- a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
+++ b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
@@ -217,7 +217,8 @@ static bool emitIntrinsic(const llvm::Record &record, llvm::raw_ostream &os) {
llvm::SmallVector<llvm::StringRef, 8> operands(intr.getNumOperands(),
"LLVM_Type");
if (requiresAccessGroup)
- operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$access_groups");
+ operands.push_back(
+ "OptionalAttr<LLVM_AccessGroupArrayAttr>:$access_groups");
if (requiresAliasAnalysis) {
operands.push_back("OptionalAttr<LLVM_AliasScopeArrayAttr>:$alias_scopes");
operands.push_back(
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