[Mlir-commits] [mlir] 365ce62 - [mlir] support unsigned int in mlir::spirv::ConstantOp::getAsmResultNames
Xiang Li
llvmlistbot at llvm.org
Mon Jan 23 09:07:18 PST 2023
Author: Xiang Li
Date: 2023-01-23T12:07:10-05:00
New Revision: 365ce62df222db60f974b0bb3f28908e87e61ada
URL: https://github.com/llvm/llvm-project/commit/365ce62df222db60f974b0bb3f28908e87e61ada
DIFF: https://github.com/llvm/llvm-project/commit/365ce62df222db60f974b0bb3f28908e87e61ada.diff
LOG: [mlir] support unsigned int in mlir::spirv::ConstantOp::getAsmResultNames
Fixes #60184 https://github.com/llvm/llvm-project/issues/60184
Differential Revision: https://reviews.llvm.org/D142295
Added:
mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-uint.mlir
Modified:
mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
Removed:
################################################################################
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
index 5e7a7feb113c7..d6346774c5d7b 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
@@ -2124,6 +2124,8 @@ void mlir::spirv::ConstantOp::getAsmResultNames(
if (intTy.isSignless()) {
specialName << intCst.getInt();
+ } else if (intTy.isUnsigned()) {
+ specialName << intCst.getUInt();
} else {
specialName << intCst.getSInt();
}
diff --git a/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-uint.mlir b/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-uint.mlir
new file mode 100644
index 0000000000000..fe17efcf6bb6d
--- /dev/null
+++ b/mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-uint.mlir
@@ -0,0 +1,8 @@
+// RUN: mlir-opt -split-input-file -convert-pdl-to-pdl-interp %s | FileCheck %s
+
+// CHECK:spirv.func @func()
+// CHECK-NEXT:%cst0_ui8 = spirv.Constant 0 : ui8
+spirv.func @func() -> () "None" {
+ %5 = spirv.Constant 0 : ui8
+ spirv.Return
+}
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