[Mlir-commits] [mlir] fcd505d - [arith] Allow integer casts of 0-D vectors

[Benjamin Kramer]

Author: Benjamin Kramer
Date: 2023-01-20T15:21:52+01:00
New Revision: fcd505d040ccc4d5ce8a4e704f36f7e605142935

URL: https://github.com/llvm/llvm-project/commit/fcd505d040ccc4d5ce8a4e704f36f7e605142935
DIFF: https://github.com/llvm/llvm-project/commit/fcd505d040ccc4d5ce8a4e704f36f7e605142935.diff

LOG: [arith] Allow integer casts of 0-D vectors

This just works, no reason to disallow it.

Differential Revision: https://reviews.llvm.org/D142137

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
    mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir

Removed: 
    


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diff  --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
index a4e542658ec77..ee38637599ed3 100644
--- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
@@ -102,7 +102,7 @@ class Arith_CastOp<string mnemonic, TypeConstraint From, TypeConstraint To,
 // excluding indices: signless integers, vectors or tensors thereof.
 def SignlessFixedWidthIntegerLike : TypeConstraint<Or<[
         AnySignlessInteger.predicate,
-        VectorOf<[AnySignlessInteger]>.predicate,
+        VectorOfAnyRankOf<[AnySignlessInteger]>.predicate,
         TensorOf<[AnySignlessInteger]>.predicate]>,
     "signless-fixed-width-integer-like">;
 

diff  --git a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
index 637f9daa1a0b3..1788232aee40c 100644
--- a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+++ b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
@@ -297,6 +297,18 @@ func.func @integer_extension_and_truncation(%arg0 : i3) {
   return
 }
 
+// CHECK-LABEL: @integer_cast_0d_vector
+func.func @integer_cast_0d_vector(%arg0 : vector<i3>) {
+// CHECK: %[[ARG0:.*]] = builtin.unrealized_conversion_cast
+// CHECK-NEXT: = llvm.sext %[[ARG0]] : vector<1xi3> to vector<1xi6>
+  %0 = arith.extsi %arg0 : vector<i3> to vector<i6>
+// CHECK-NEXT: = llvm.zext %[[ARG0]] : vector<1xi3> to vector<1xi6>
+  %1 = arith.extui %arg0 : vector<i3> to vector<i6>
+// CHECK-NEXT: = llvm.trunc %[[ARG0]] : vector<1xi3> to vector<1xi2>
+  %2 = arith.trunci %arg0 : vector<i3> to vector<i2>
+  return
+}
+
 // CHECK-LABEL: func @fcmp(%arg0: f32, %arg1: f32) {
 func.func @fcmp(f32, f32) -> () {
 ^bb0(%arg0: f32, %arg1: f32):