[Mlir-commits] [mlir] cbde212 - Use APInt::popcount instead of APInt::countPopulation (NFC)
Kazu Hirata
llvmlistbot at llvm.org
Sun Feb 19 11:29:20 PST 2023
Author: Kazu Hirata
Date: 2023-02-19T11:29:12-08:00
New Revision: cbde2124f153f8fd084e8ff1221c0357442ea707
URL: https://github.com/llvm/llvm-project/commit/cbde2124f153f8fd084e8ff1221c0357442ea707
DIFF: https://github.com/llvm/llvm-project/commit/cbde2124f153f8fd084e8ff1221c0357442ea707.diff
LOG: Use APInt::popcount instead of APInt::countPopulation (NFC)
This is for consistency with the C++20-style bit manipulation
functions in <bit>.
Added:
Modified:
clang/lib/AST/ExprConstant.cpp
llvm/include/llvm/ADT/APInt.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/include/llvm/Support/KnownBits.h
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/lib/Transforms/Utils/Local.cpp
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/utils/TableGen/CodeGenSchedule.cpp
mlir/lib/Dialect/Math/IR/MathOps.cpp
Removed:
################################################################################
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 3e2164c4eebc8..e44aa546aae6c 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -12142,7 +12142,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!EvaluateInteger(E->getArg(0), Val, Info))
return false;
- return Success(Val.countPopulation() % 2, E);
+ return Success(Val.popcount() % 2, E);
}
case Builtin::BI__builtin_popcount:
@@ -12152,7 +12152,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
if (!EvaluateInteger(E->getArg(0), Val, Info))
return false;
- return Success(Val.countPopulation(), E);
+ return Success(Val.popcount(), E);
}
case Builtin::BI__builtin_rotateleft8:
diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h
index 948e3f71ddae3..aa78d648c46a7 100644
--- a/llvm/include/llvm/ADT/APInt.h
+++ b/llvm/include/llvm/ADT/APInt.h
@@ -347,7 +347,7 @@ class [[nodiscard]] APInt {
///
/// \returns true if this APInt only has the specified bit set.
bool isOneBitSet(unsigned BitNo) const {
- return (*this)[BitNo] && countPopulation() == 1;
+ return (*this)[BitNo] && popcount() == 1;
}
/// Determine if all bits are set. This is true for zero-width values.
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index ce1caafb92fb9..02eff6ad1e1ed 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1508,7 +1508,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
// SelectionDAGBuilder.
APInt Exponent = RHSC->getValue().abs();
unsigned ActiveBits = Exponent.getActiveBits();
- unsigned PopCount = Exponent.countPopulation();
+ unsigned PopCount = Exponent.popcount();
InstructionCost Cost = (ActiveBits + PopCount - 2) *
thisT()->getArithmeticInstrCost(
Instruction::FMul, RetTy, CostKind);
diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h
index 83b962a11ea34..caa0aef93e028 100644
--- a/llvm/include/llvm/Support/KnownBits.h
+++ b/llvm/include/llvm/Support/KnownBits.h
@@ -49,7 +49,7 @@ struct KnownBits {
/// Returns true if we know the value of all bits.
bool isConstant() const {
assert(!hasConflict() && "KnownBits conflict!");
- return Zero.countPopulation() + One.countPopulation() == getBitWidth();
+ return Zero.popcount() + One.popcount() == getBitWidth();
}
/// Returns the value when all bits have a known value. This just returns One
@@ -290,13 +290,11 @@ struct KnownBits {
}
/// Returns the number of bits known to be one.
- unsigned countMinPopulation() const {
- return One.countPopulation();
- }
+ unsigned countMinPopulation() const { return One.popcount(); }
/// Returns the maximum number of bits that could be one.
unsigned countMaxPopulation() const {
- return getBitWidth() - Zero.countPopulation();
+ return getBitWidth() - Zero.popcount();
}
/// Returns the maximum number of bits needed to represent all possible
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index a43402d2b62ce..5a6490a4ca13c 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -2395,7 +2395,7 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
case Intrinsic::bswap:
return ConstantInt::get(Ty->getContext(), Op->getValue().byteSwap());
case Intrinsic::ctpop:
- return ConstantInt::get(Ty, Op->getValue().countPopulation());
+ return ConstantInt::get(Ty, Op->getValue().popcount());
case Intrinsic::bitreverse:
return ConstantInt::get(Ty->getContext(), Op->getValue().reverseBits());
case Intrinsic::convert_from_fp16: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b436e0ddec73e..7a1520cf6967e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18187,7 +18187,7 @@ struct LoadedSlice {
/// Get the size of the slice to be loaded in bytes.
unsigned getLoadedSize() const {
- unsigned SliceSize = getUsedBits().countPopulation();
+ unsigned SliceSize = getUsedBits().popcount();
assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
return SliceSize / 8;
}
@@ -24034,7 +24034,7 @@ static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf,
assert((unsigned)Idx < NumElts && "Out-of-bounds shuffle indice?");
DemandedElts.setBit(Idx);
}
- assert(DemandedElts.countPopulation() > 1 && "Is a splat shuffle already?");
+ assert(DemandedElts.popcount() > 1 && "Is a splat shuffle already?");
APInt UndefElts;
if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) {
// Even if all demanded elements are splat, some of them could be undef.
@@ -26109,7 +26109,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
SDValue AndLHS = N0->getOperand(0);
auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
- if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
+ if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) {
// Shift the tested bit over the sign bit.
const APInt &AndMask = ConstAndRHS->getAPIntValue();
unsigned ShCt = AndMask.getBitWidth() - 1;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0cbca37e93424..457901099018b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2714,7 +2714,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
// TODO: Handle source ops splats with undefs.
auto CheckSplatSrc = [&](SDValue Src, const APInt &SrcElts) {
APInt SrcUndefs;
- return (SrcElts.countPopulation() == 1) ||
+ return (SrcElts.popcount() == 1) ||
(isSplatValue(Src, SrcElts, SrcUndefs, Depth + 1) &&
(SrcElts & SrcUndefs).isZero());
};
@@ -5264,7 +5264,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return getConstant(Val.byteSwap(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTPOP:
- return getConstant(Val.countPopulation(), DL, VT, C->isTargetOpcode(),
+ return getConstant(Val.popcount(), DL, VT, C->isTargetOpcode(),
C->isOpaque());
case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 2eb3101345c06..de31715f5d878 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -3149,7 +3149,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
// BFI/BFXIL dst, src, #lsb, #width.
int LSB = llvm::countr_one(NotKnownZero);
- int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
+ int Width = BitWidth - APInt(BitWidth, NotKnownZero).popcount();
// BFI/BFXIL is an alias of BFM, so translate to BFM operands.
unsigned ImmR = (BitWidth - LSB) % BitWidth;
@@ -3505,7 +3505,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
SDValue Src = And1->getOperand(0);
SDValue Dst = And0->getOperand(0);
unsigned LSB = llvm::countr_zero(Mask1Imm);
- int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
+ int Width = BitWidth - APInt(BitWidth, Mask0Imm).popcount();
// The BFXIL inserts the low-order bits from a source register, so right
// shift the needed bits into place.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 687ff6d29bf1e..8e6180a2b2764 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2115,7 +2115,7 @@ bool AArch64TargetLowering::targetShrinkDemandedConstant(
"i32 or i64 is expected after legalization.");
// Exit early if we demand all bits.
- if (DemandedBits.countPopulation() == Size)
+ if (DemandedBits.popcount() == Size)
return false;
unsigned NewOpc;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index a50511ef3e6df..2b9592d5028d6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -1152,7 +1152,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal);
}
- unsigned NewNumElts = DemandedElts.countPopulation();
+ unsigned NewNumElts = DemandedElts.popcount();
if (!NewNumElts)
return UndefValue::get(IIVTy);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 485dabc71c62e..4ef3c7972b736 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -5031,7 +5031,7 @@ void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
int OpIdx) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
"Expected G_CONSTANT");
- MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation());
+ MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount());
}
/// This only really exists to satisfy DAG type checking machinery, so is a
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index b09d0f0689d3e..2450fa7360d2c 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -3542,7 +3542,7 @@ static std::optional<std::pair<unsigned, unsigned>>
getContiguousRangeOfSetBits(const APInt &A) {
unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
unsigned LastOne = A.countTrailingZeros();
- if (A.countPopulation() != (FirstOne - LastOne + 1))
+ if (A.popcount() != (FirstOne - LastOne + 1))
return std::nullopt;
return std::make_pair(FirstOne, LastOne);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 8a5e37a7adfd3..c8e133e7483b6 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14687,7 +14687,7 @@ static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
SDValue From = N->getOperand(1);
ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
- FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
+ FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.popcount());
// If the Base came from a SHR #C, we can deduce that it is really testing bit
// #C in the base of the SHR.
@@ -17915,7 +17915,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
// Now, is it profitable to continue?
APInt OrCI = OrC->getAPIntValue();
unsigned Heuristic = Subtarget->isThumb() ? 3 : 2;
- if (OrCI.countPopulation() > Heuristic)
+ if (OrCI.popcount() > Heuristic)
return SDValue();
// Lastly, can we determine that the bits defined by OrCI
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index df357506b34f2..1cd4c6caf86fc 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -670,8 +670,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
// as the original value.
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}
@@ -702,8 +701,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
// Extract the run of set bits starting with bit zero, and test that the
// result is the same as the original value
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 025de71ea5edc..0ba8264c71957 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9401,14 +9401,14 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
LoadMask.setBit(i);
LastLoadedElt = i;
}
- assert((ZeroMask.countPopulation() + UndefMask.countPopulation() +
- LoadMask.countPopulation()) == NumElems &&
+ assert((ZeroMask.popcount() + UndefMask.popcount() + LoadMask.popcount()) ==
+ NumElems &&
"Incomplete element masks");
// Handle Special Cases - all undef or undef/zero.
- if (UndefMask.countPopulation() == NumElems)
+ if (UndefMask.popcount() == NumElems)
return DAG.getUNDEF(VT);
- if ((ZeroMask.countPopulation() + UndefMask.countPopulation()) == NumElems)
+ if ((ZeroMask.popcount() + UndefMask.popcount()) == NumElems)
return VT.isInteger() ? DAG.getConstant(0, DL, VT)
: DAG.getConstantFP(0.0, DL, VT);
@@ -11269,7 +11269,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
// our source BUILD_VECTOR, create another FREEZE-UNDEF splat BUILD_VECTOR,
// and blend the FREEZE-UNDEF operands back in.
// FIXME: is this worthwhile even for a single FREEZE-UNDEF operand?
- if (unsigned NumFrozenUndefElts = FrozenUndefMask.countPopulation();
+ if (unsigned NumFrozenUndefElts = FrozenUndefMask.popcount();
NumFrozenUndefElts >= 2 && NumFrozenUndefElts < NumElems) {
SmallVector<int, 16> BlendMask(NumElems, -1);
SmallVector<SDValue, 16> Elts(NumElems, DAG.getUNDEF(OpEltVT));
@@ -11320,8 +11320,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (SDValue BitOp = lowerBuildVectorToBitOp(BV, Subtarget, DAG))
return BitOp;
- unsigned NumZero = ZeroMask.countPopulation();
- unsigned NumNonZero = NonZeroMask.countPopulation();
+ unsigned NumZero = ZeroMask.popcount();
+ unsigned NumNonZero = NonZeroMask.popcount();
// If we are inserting one variable into a vector of non-zero constants, try
// to avoid loading each constant element as a scalar. Load the constants as a
@@ -38089,7 +38089,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
case X86ISD::PEXT: {
Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
// The result has as many leading zeros as the number of zeroes in the mask.
- unsigned Count = Known.Zero.countPopulation();
+ unsigned Count = Known.Zero.popcount();
Known.Zero = APInt::getHighBitsSet(BitWidth, Count);
Known.One.clearAllBits();
break;
@@ -43298,7 +43298,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
// operand 0 used. Undemanded bits from the mask don't matter so filter
// them before counting.
KnownBits Known2;
- uint64_t Count = (~Known.Zero & LoMask).countPopulation();
+ uint64_t Count = (~Known.Zero & LoMask).popcount();
APInt DemandedMask(APInt::getLowBitsSet(BitWidth, Count));
if (SimplifyDemandedBits(Op0, DemandedMask, Known2, TLO, Depth + 1))
return true;
@@ -43411,7 +43411,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
if (IdentityOp == 0)
break;
}
- assert((IdentityOp == 0 || IdentityOp.countPopulation() == 1) &&
+ assert((IdentityOp == 0 || IdentityOp.popcount() == 1) &&
"Multiple identity shuffles detected");
if (IdentityOp != 0)
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 9366c1b3d0d98..f381649a5e7d5 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4502,7 +4502,7 @@ X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
// series of UNPCK followed by CONCAT_VECTORS - all of these can be
// considered cheap.
if (Ty->isIntOrIntVectorTy())
- Cost += DemandedElts.countPopulation();
+ Cost += DemandedElts.popcount();
// Get the smaller of the legalized or original pow2-extended number of
// vector elements, which represents the number of unpacks we'll end up
@@ -4667,7 +4667,7 @@ X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
// then we won't need to do that shuffle, so adjust the cost accordingly.
APInt DemandedDstVectors = APIntOps::ScaleBitMask(
DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
- unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation();
+ unsigned NumDstVectorsDemanded = DemandedDstVectors.popcount();
InstructionCost SingleShuffleCost = getShuffleCost(
TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/std::nullopt, CostKind,
@@ -4813,7 +4813,7 @@ InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
APInt DemandedElts =
APInt::getBitsSet(CoalescedVecTy->getNumElements(),
CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
- assert(DemandedElts.countPopulation() == 1 && "Inserting single value");
+ assert(DemandedElts.popcount() == 1 && "Inserting single value");
Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
!IsLoad, CostKind);
}
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 77d6754229662..ee75279ec7218 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1653,7 +1653,7 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
// corresponding input elements are undef.
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
- if (SubUndef.countPopulation() == Ratio)
+ if (SubUndef.popcount() == Ratio)
UndefElts.setBit(OutIdx);
}
} else {
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index ddef654ca73cc..2ca25ef104813 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -3152,7 +3152,7 @@ collectBitParts(Value *V, bool MatchBSwaps, bool MatchBitReversals,
// Check that the mask allows a multiple of 8 bits for a bswap, for an
// early exit.
- unsigned NumMaskedBits = AndMask.countPopulation();
+ unsigned NumMaskedBits = AndMask.popcount();
if (!MatchBitReversals && (NumMaskedBits % 8) != 0)
return Result;
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 372a6698ce8ac..73b3bb3f454ee 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -5469,7 +5469,7 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU,
bool HasDefault =
!isa<UnreachableInst>(SI->getDefaultDest()->getFirstNonPHIOrDbg());
const unsigned NumUnknownBits =
- Known.getBitWidth() - (Known.Zero | Known.One).countPopulation();
+ Known.getBitWidth() - (Known.Zero | Known.One).popcount();
assert(NumUnknownBits <= Known.getBitWidth());
if (HasDefault && DeadCases.empty() &&
NumUnknownBits < 64 /* avoid overflow */ &&
@@ -5860,7 +5860,7 @@ static Value *foldSwitchToSelect(const SwitchCaseResultVectorTy &ResultVector,
// Check if cases with the same result can cover all number
// in touched bits.
- if (BitMask.countPopulation() == Log2_32(CaseCount)) {
+ if (BitMask.popcount() == Log2_32(CaseCount)) {
if (!MinCaseVal->isNullValue())
Condition = Builder.CreateSub(Condition, MinCaseVal);
Value *And = Builder.CreateAnd(Condition, ~BitMask, "switch.and");
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 441a088c17315..117abc9b4f389 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -370,8 +370,8 @@ processSTIPredicate(STIPredicateFunction &Fn,
const std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
auto LessThan = [](const APInt &Lhs, const APInt &Rhs) {
- unsigned LhsCountPopulation = Lhs.countPopulation();
- unsigned RhsCountPopulation = Rhs.countPopulation();
+ unsigned LhsCountPopulation = Lhs.popcount();
+ unsigned RhsCountPopulation = Rhs.popcount();
return ((LhsCountPopulation < RhsCountPopulation) ||
((LhsCountPopulation == RhsCountPopulation) &&
(Lhs.countLeadingZeros() > Rhs.countLeadingZeros())));
diff --git a/mlir/lib/Dialect/Math/IR/MathOps.cpp b/mlir/lib/Dialect/Math/IR/MathOps.cpp
index 0dc041420e9e9..194ba9f234534 100644
--- a/mlir/lib/Dialect/Math/IR/MathOps.cpp
+++ b/mlir/lib/Dialect/Math/IR/MathOps.cpp
@@ -171,9 +171,8 @@ OpFoldResult math::CountTrailingZerosOp::fold(FoldAdaptor adaptor) {
OpFoldResult math::CtPopOp::fold(FoldAdaptor adaptor) {
return constFoldUnaryOp<IntegerAttr>(
- adaptor.getOperands(), [](const APInt &a) {
- return APInt(a.getBitWidth(), a.countPopulation());
- });
+ adaptor.getOperands(),
+ [](const APInt &a) { return APInt(a.getBitWidth(), a.popcount()); });
}
//===----------------------------------------------------------------------===//
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