[Mlir-commits] [mlir] 7f249e4 - [milr][llvm] Add remaining loop metadata support
Christian Ulmann
llvmlistbot at llvm.org
Mon Feb 13 00:21:59 PST 2023
Author: Christian Ulmann
Date: 2023-02-13T09:09:22+01:00
New Revision: 7f249e45eca41dd6030d4600c40a40033afce603
URL: https://github.com/llvm/llvm-project/commit/7f249e45eca41dd6030d4600c40a40033afce603
DIFF: https://github.com/llvm/llvm-project/commit/7f249e45eca41dd6030d4600c40a40033afce603.diff
LOG: [milr][llvm] Add remaining loop metadata support
This commit adds support for the last two loop metadata nodes produced
anywhere in the llvm-project.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D143746
Added:
Modified:
mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
mlir/test/Dialect/LLVMIR/loop-metadata.mlir
mlir/test/Target/LLVMIR/Import/metadata-loop.ll
mlir/test/Target/LLVMIR/loop-metadata.mlir
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
index 06783b161bf5..a6d8c703baaf 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
@@ -168,6 +168,32 @@ def LoopPipelineAttr : LLVM_Attr<"LoopPipeline", "loop_pipeline"> {
let assemblyFormat = "`<` struct(params) `>`";
}
+def LoopPeeledAttr : LLVM_Attr<"LoopPeeled", "loop_peeled"> {
+ let description = [{
+ This attribute defines pipelining specific loop annotations that map to
+ the "!llvm.loop.peeled" metadata.
+ }];
+
+ let parameters = (ins
+ OptionalParameter<"IntegerAttr">:$count
+ );
+
+ let assemblyFormat = "`<` struct(params) `>`";
+}
+
+def LoopUnswitchAttr : LLVM_Attr<"LoopUnswitch", "loop_unswitch"> {
+ let description = [{
+ This attribute defines pipelining specific loop annotations that map to
+ the "!llvm.loop.unswitch" metadata.
+ }];
+
+ let parameters = (ins
+ OptionalParameter<"BoolAttr">:$partialDisable
+ );
+
+ let assemblyFormat = "`<` struct(params) `>`";
+}
+
def LoopAnnotationAttr : LLVM_Attr<"LoopAnnotation", "loop_annotation"> {
let description = [{
This attributes encapsulates "loop metadata". It is meant to decorate
@@ -186,6 +212,8 @@ def LoopAnnotationAttr : LLVM_Attr<"LoopAnnotation", "loop_annotation"> {
OptionalParameter<"LoopLICMAttr">:$licm,
OptionalParameter<"LoopDistributeAttr">:$distribute,
OptionalParameter<"LoopPipelineAttr">:$pipeline,
+ OptionalParameter<"LoopPeeledAttr">:$peeled,
+ OptionalParameter<"LoopUnswitchAttr">:$unswitch,
OptionalParameter<"BoolAttr">:$mustProgress,
OptionalParameter<"BoolAttr">:$isVectorized,
OptionalArrayRefParameter<"SymbolRefAttr">:$parallelAccesses
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index c19d268d745f..8d654df7d217 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -2666,10 +2666,11 @@ struct LLVMOpAsmDialectInterface : public OpAsmDialectInterface {
DISubprogramAttr, DISubroutineTypeAttr, LoopAnnotationAttr,
LoopVectorizeAttr, LoopInterleaveAttr, LoopUnrollAttr,
LoopUnrollAndJamAttr, LoopLICMAttr, LoopDistributeAttr,
- LoopPipelineAttr>([&](auto attr) {
- os << decltype(attr)::getMnemonic();
- return AliasResult::OverridableAlias;
- })
+ LoopPipelineAttr, LoopPeeledAttr, LoopUnswitchAttr>(
+ [&](auto attr) {
+ os << decltype(attr)::getMnemonic();
+ return AliasResult::OverridableAlias;
+ })
.Default([](Attribute) { return AliasResult::NoAlias; });
}
};
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
index 53e6f9c50e89..2986b64538c2 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
@@ -50,6 +50,8 @@ struct LoopMetadataConversion {
FailureOr<LoopLICMAttr> convertLICMAttr();
FailureOr<LoopDistributeAttr> convertDistributeAttr();
FailureOr<LoopPipelineAttr> convertPipelineAttr();
+ FailureOr<LoopPeeledAttr> convertPeeledAttr();
+ FailureOr<LoopUnswitchAttr> convertUnswitchAttr();
FailureOr<SmallVector<SymbolRefAttr>> convertParallelAccesses();
llvm::StringMap<const llvm::MDNode *> propertyMap;
@@ -373,6 +375,17 @@ FailureOr<LoopPipelineAttr> LoopMetadataConversion::convertPipelineAttr() {
return createIfNonNull<LoopPipelineAttr>(ctx, disable, initiationinterval);
}
+FailureOr<LoopPeeledAttr> LoopMetadataConversion::convertPeeledAttr() {
+ FailureOr<IntegerAttr> count = lookupIntNode("llvm.loop.peeled.count");
+ return createIfNonNull<LoopPeeledAttr>(ctx, count);
+}
+
+FailureOr<LoopUnswitchAttr> LoopMetadataConversion::convertUnswitchAttr() {
+ FailureOr<BoolAttr> partialDisable =
+ lookupUnitNode("llvm.loop.unswitch.partial.disable");
+ return createIfNonNull<LoopUnswitchAttr>(ctx, partialDisable);
+}
+
FailureOr<SmallVector<SymbolRefAttr>>
LoopMetadataConversion::convertParallelAccesses() {
FailureOr<SmallVector<llvm::MDNode *>> nodes =
@@ -403,6 +416,8 @@ LoopAnnotationAttr LoopMetadataConversion::convert() {
FailureOr<LoopLICMAttr> licmAttr = convertLICMAttr();
FailureOr<LoopDistributeAttr> distributeAttr = convertDistributeAttr();
FailureOr<LoopPipelineAttr> pipelineAttr = convertPipelineAttr();
+ FailureOr<LoopPeeledAttr> peeledAttr = convertPeeledAttr();
+ FailureOr<LoopUnswitchAttr> unswitchAttr = convertUnswitchAttr();
FailureOr<BoolAttr> mustProgress = lookupUnitNode("llvm.loop.mustprogress");
FailureOr<BoolAttr> isVectorized =
lookupIntNodeAsBoolAttr("llvm.loop.isvectorized");
@@ -418,8 +433,8 @@ LoopAnnotationAttr LoopMetadataConversion::convert() {
return createIfNonNull<LoopAnnotationAttr>(
ctx, disableNonForced, vecAttr, interleaveAttr, unrollAttr,
- unrollAndJamAttr, licmAttr, distributeAttr, pipelineAttr, mustProgress,
- isVectorized, parallelAccesses);
+ unrollAndJamAttr, licmAttr, distributeAttr, pipelineAttr, peeledAttr,
+ unswitchAttr, mustProgress, isVectorized, parallelAccesses);
}
LoopAnnotationAttr
diff --git a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
index b02433b33edf..5f27f97f2fd4 100644
--- a/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
@@ -42,6 +42,8 @@ struct LoopAnnotationConversion {
void convertLoopOptions(LoopLICMAttr options);
void convertLoopOptions(LoopDistributeAttr options);
void convertLoopOptions(LoopPipelineAttr options);
+ void convertLoopOptions(LoopPeeledAttr options);
+ void convertLoopOptions(LoopUnswitchAttr options);
LoopAnnotationAttr attr;
ModuleTranslation &moduleTranslation;
@@ -176,6 +178,15 @@ void LoopAnnotationConversion::convertLoopOptions(LoopPipelineAttr options) {
options.getInitiationinterval());
}
+void LoopAnnotationConversion::convertLoopOptions(LoopPeeledAttr options) {
+ convertI32Node("llvm.loop.peeled.count", options.getCount());
+}
+
+void LoopAnnotationConversion::convertLoopOptions(LoopUnswitchAttr options) {
+ addUnitNode("llvm.loop.unswitch.partial.disable",
+ options.getPartialDisable());
+}
+
llvm::MDNode *LoopAnnotationConversion::convert() {
// Reserve operand 0 for loop id self reference.
@@ -202,6 +213,10 @@ llvm::MDNode *LoopAnnotationConversion::convert() {
convertLoopOptions(options);
if (auto options = attr.getPipeline())
convertLoopOptions(options);
+ if (auto options = attr.getPeeled())
+ convertLoopOptions(options);
+ if (auto options = attr.getUnswitch())
+ convertLoopOptions(options);
ArrayRef<SymbolRefAttr> parallelAccessGroups = attr.getParallelAccesses();
if (!parallelAccessGroups.empty()) {
diff --git a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
index 0d434323f870..8841a1fad918 100644
--- a/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Dialect/LLVMIR/loop-metadata.mlir
@@ -36,6 +36,12 @@
// CHECK-DAG: #[[PIPELINE:.*]] = #llvm.loop_pipeline<disable = true, initiationinterval = 1 : i32>
#pipeline = #llvm.loop_pipeline<disable = true, initiationinterval = 1 : i32>
+// CHECK-DAG: #[[PEELED:.*]] = #llvm.loop_peeled<count = 8 : i32>
+#peeled = #llvm.loop_peeled<count = 8 : i32>
+
+// CHECK-DAG: #[[UNSWITCH:.*]] = #llvm.loop_unswitch<partialDisable = true>
+#unswitch = #llvm.loop_unswitch<partialDisable = true>
+
// CHECK: #[[LOOP_ANNOT:.*]] = #llvm.loop_annotation<
// CHECK-DAG: disableNonforced = false
// CHECK-DAG: mustProgress = true
@@ -44,6 +50,8 @@
// CHECK-DAG: licm = #[[LICM]]
// CHECK-DAG: distribute = #[[DISTRIBUTE]]
// CHECK-DAG: pipeline = #[[PIPELINE]]
+// CHECK-DAG: peeled = #[[PEELED]]
+// CHECK-DAG: unswitch = #[[UNSWITCH]]
// CHECK-DAG: isVectorized = false
// CHECK-DAG: parallelAccesses = @metadata::@group1, @metadata::@group2>
#loopMD = #llvm.loop_annotation<disableNonforced = false,
@@ -55,6 +63,8 @@
licm = #licm,
distribute = #distribute,
pipeline = #pipeline,
+ peeled = #peeled,
+ unswitch = #unswitch,
isVectorized = false,
parallelAccesses = @metadata::@group1, @metadata::@group2>
diff --git a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
index 9aecb13c0095..315852663dd0 100644
--- a/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
+++ b/mlir/test/Target/LLVMIR/Import/metadata-loop.ll
@@ -221,6 +221,40 @@ end:
; // -----
+; CHECK-DAG: #[[PEELED_ATTR:.*]] = #llvm.loop_peeled<count = 5 : i32>
+; CHECK-DAG: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<peeled = #[[PEELED_ATTR]]>
+
+; CHECK-LABEL: @peeled
+define void @peeled(i64 %n, ptr %A) {
+entry:
+; CHECK: llvm.br ^{{.*}} {llvm.loop = #[[$ANNOT_ATTR]]}
+ br label %end, !llvm.loop !1
+end:
+ ret void
+}
+
+!1 = distinct !{!1, !2}
+!2 = !{!"llvm.loop.peeled.count", i32 5}
+
+; // -----
+
+; CHECK-DAG: #[[UNSWITCH_ATTR:.*]] = #llvm.loop_unswitch<partialDisable = true>
+; CHECK-DAG: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<unswitch = #[[UNSWITCH_ATTR]]>
+
+; CHECK-LABEL: @unswitched
+define void @unswitched(i64 %n, ptr %A) {
+entry:
+; CHECK: llvm.br ^{{.*}} {llvm.loop = #[[$ANNOT_ATTR]]}
+ br label %end, !llvm.loop !1
+end:
+ ret void
+}
+
+!1 = distinct !{!1, !2}
+!2 = !{!"llvm.loop.unswitch.partial.disable"}
+
+; // -----
+
; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = @__llvm_global_metadata::@[[GROUP0:.*]]>
; CHECK: llvm.metadata @__llvm_global_metadata {
diff --git a/mlir/test/Target/LLVMIR/loop-metadata.mlir b/mlir/test/Target/LLVMIR/loop-metadata.mlir
index 9bed3ae39162..e7d06775bf9f 100644
--- a/mlir/test/Target/LLVMIR/loop-metadata.mlir
+++ b/mlir/test/Target/LLVMIR/loop-metadata.mlir
@@ -207,6 +207,32 @@ llvm.func @pipelineOptions() {
// -----
+// CHECK-LABEL: @peeledOptions
+llvm.func @peeledOptions() {
+ // CHECK: br {{.*}} !llvm.loop ![[LOOP_NODE:[0-9]+]]
+ llvm.br ^bb1 {llvm.loop = #llvm.loop_annotation<peeled = <count = 3 : i32>>}
+^bb1:
+ llvm.return
+}
+
+// CHECK: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}}
+// CHECK-DAG: ![[VEC_NODE0:[0-9]+]] = !{!"llvm.loop.peeled.count", i32 3}
+
+// -----
+
+// CHECK-LABEL: @unswitchOptions
+llvm.func @unswitchOptions() {
+ // CHECK: br {{.*}} !llvm.loop ![[LOOP_NODE:[0-9]+]]
+ llvm.br ^bb1 {llvm.loop = #llvm.loop_annotation<unswitch = <partialDisable = true>>}
+^bb1:
+ llvm.return
+}
+
+// CHECK: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}}
+// CHECK-DAG: ![[VEC_NODE0:[0-9]+]] = !{!"llvm.loop.unswitch.partial.disable"}
+
+// -----
+
// CHECK-LABEL: @loopOptions
llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) {
%0 = llvm.mlir.constant(0 : i32) : i32
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