[Mlir-commits] [mlir] [mlir][vector] `LoadOp`/`StoreOp`: Allow 0-D vectors (PR #76134)

[Cullen Rhodes]

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@@ -714,6 +714,16 @@ func.func @flat_transpose_int(%arg0: vector<16xi32>) -> vector<16xi32> {
   return %0 : vector<16xi32>
 }
 
+// CHECK-LABEL: @vector_load_and_store_0d_scalar_memref
+func.func @vector_load_and_store_0d_scalar_memref(%memref : memref<200x100xf32>,
+                                                  %i : index, %j : index) {
+  // CHECK: %[[ld:.*]] = vector.load %{{.*}}[%{{.*}}] : memref<200x100xf32>, vector<f32>
+  %0 = vector.load %memref[%i, %j] : memref<200x100xf32>, vector<f32>
+  // CHECK: vector.store %[[ld]], %{{.*}}[%{{.*}}] : memref<200x100xf32>, vector<f32>
+  vector.store %0, %memref[%i, %j] : memref<200x100xf32>, vector<f32>
----------------
c-rhodes wrote:

> I was told that that's intentional (so that `vector.load` and `vector.store` look similar).

I see, it's a bit inconsistent w.r.t to `transfer_read` / `transfer_write` where the types order matches the inputs.

> Also not a fan, but that's tangential to this PR.

Of course


https://github.com/llvm/llvm-project/pull/76134