[Mlir-commits] [mlir] [mlir][amdgpu] Shared memory access optimization pass (PR #75627)
Mehdi Amini
llvmlistbot at llvm.org
Tue Dec 19 03:00:52 PST 2023
================
@@ -43,6 +43,21 @@ void AMDGPUDialect::initialize() {
>();
}
+bool amdgpu::AMDGPUDialect::isSharedMemoryAddressSpace(Attribute memorySpace) {
+ if (!memorySpace)
+ return false;
+ if (auto intAttr = llvm::dyn_cast<IntegerAttr>(memorySpace))
+ return intAttr.getInt() == AMDGPUDialect::kSharedMemoryAddressSpace;
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joker-eph wrote:
Other than at the LLVM level, I wouldn't think we'll have integer based memory spaces.
https://github.com/llvm/llvm-project/pull/75627
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