[Mlir-commits] [mlir] [mlir][vector] Add patterns for vector masked load/store (PR #74834)

[Jakub Kuderski]

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@@ -0,0 +1,95 @@
+// RUN: mlir-opt %s --test-vector-emulate-masked-load-store | FileCheck %s
+
+// CHECK-LABEL:  @vector_maskedload
+//  CHECK-SAME:  (%[[ARG0:.*]]: memref<4x5xf32, #spirv.storage_class<StorageBuffer>>) -> vector<4xf32> {
+//       CHECK:  %[[CST:.*]] = arith.constant dense<0.000000e+00> : vector<4xf32>
+//       CHECK:  %[[C7:.*]] = arith.constant 7 : index
+//       CHECK:  %[[C6:.*]] = arith.constant 6 : index
+//       CHECK:  %[[C5:.*]] = arith.constant 5 : index
+//       CHECK:  %[[C0:.*]] = arith.constant 0 : index
+//       CHECK:  %[[C1:.*]] = arith.constant 1 : index
+//       CHECK:  %[[C4:.*]] = arith.constant 4 : index
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kuhar wrote:

We match ops whose order doesn't matter with `CHECK-DAG` to make this more robust against instruction ordering changes

https://github.com/llvm/llvm-project/pull/74834