[Mlir-commits] [mlir] [MLIR][RISCV] Add VCIX dialect (PR #74780)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu Dec 7 15:24:57 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: Kolya Panchenko (nikolaypanchenko)
<details>
<summary>Changes</summary>
The changeset adds new dialect called VCIX to support VCIX intrinsics of XSfvcp extension to allow MLIR users to interact with co-processors that are compatible with that extension.
Source: https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
---
Patch is 54.03 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/74780.diff
16 Files Affected:
- (modified) mlir/include/mlir/Conversion/Passes.td (+4-1)
- (modified) mlir/include/mlir/Dialect/CMakeLists.txt (+1)
- (added) mlir/include/mlir/Dialect/VCIX/CMakeLists.txt (+8)
- (added) mlir/include/mlir/Dialect/VCIX/VCIX.td (+305)
- (added) mlir/include/mlir/Dialect/VCIX/VCIXAttrs.h (+20)
- (added) mlir/include/mlir/Dialect/VCIX/VCIXAttrs.td (+91)
- (added) mlir/include/mlir/Dialect/VCIX/VCIXDialect.h (+28)
- (modified) mlir/include/mlir/InitAllDialects.h (+2)
- (modified) mlir/lib/Dialect/CMakeLists.txt (+1)
- (added) mlir/lib/Dialect/VCIX/CMakeLists.txt (+1)
- (added) mlir/lib/Dialect/VCIX/IR/CMakeLists.txt (+16)
- (added) mlir/lib/Dialect/VCIX/IR/VCIXAttrs.cpp (+12)
- (added) mlir/lib/Dialect/VCIX/IR/VCIXDialect.cpp (+28)
- (added) mlir/lib/Dialect/VCIX/IR/VCIXOps.cpp (+174)
- (added) mlir/test/Dialect/VCIX/invalid.mlir (+57)
- (added) mlir/test/Dialect/VCIX/ops.mlir (+531)
``````````diff
diff --git a/mlir/include/mlir/Conversion/Passes.td b/mlir/include/mlir/Conversion/Passes.td
index 06756ff3df0bb3..c03b0137e6e0f5 100644
--- a/mlir/include/mlir/Conversion/Passes.td
+++ b/mlir/include/mlir/Conversion/Passes.td
@@ -1294,6 +1294,10 @@ def ConvertVectorToLLVMPass : Pass<"convert-vector-to-llvm"> {
"bool", /*default=*/"false",
"Enables the use of ArmSVE dialect while lowering the vector "
"dialect.">,
+ Option<"vcix", "enable-vcix",
+ "bool", /*default=*/"false",
+ "Enables the use of VCIX dialect while lowering the vector "
+ "dialect to RISC-V target">,
Option<"x86Vector", "enable-x86vector",
"bool", /*default=*/"false",
"Enables the use of X86Vector dialect while lowering the vector "
@@ -1310,5 +1314,4 @@ def ConvertVectorToSPIRV : Pass<"convert-vector-to-spirv"> {
let constructor = "mlir::createConvertVectorToSPIRVPass()";
let dependentDialects = ["spirv::SPIRVDialect"];
}
-
#endif // MLIR_CONVERSION_PASSES
diff --git a/mlir/include/mlir/Dialect/CMakeLists.txt b/mlir/include/mlir/Dialect/CMakeLists.txt
index 1c4569ecfa5848..1408ced218dbb2 100644
--- a/mlir/include/mlir/Dialect/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/CMakeLists.txt
@@ -37,5 +37,6 @@ add_subdirectory(Tosa)
add_subdirectory(Transform)
add_subdirectory(UB)
add_subdirectory(Utils)
+add_subdirectory(VCIX)
add_subdirectory(Vector)
add_subdirectory(X86Vector)
diff --git a/mlir/include/mlir/Dialect/VCIX/CMakeLists.txt b/mlir/include/mlir/Dialect/VCIX/CMakeLists.txt
new file mode 100644
index 00000000000000..2ed490283b3519
--- /dev/null
+++ b/mlir/include/mlir/Dialect/VCIX/CMakeLists.txt
@@ -0,0 +1,8 @@
+add_mlir_dialect(VCIX vcix)
+add_mlir_doc(VCIXOps VCIXOps Dialects/ -gen-dialect-doc -dialect=vcix)
+
+set(LLVM_TARGET_DEFINITIONS VCIXAttrs.td)
+mlir_tablegen(VCIXDialectEnums.h.inc -gen-enum-decls)
+mlir_tablegen(VCIXDialectEnums.cpp.inc -gen-enum-defs)
+add_public_tablegen_target(MLIRVCIXDialectEnumIncGen)
+add_dependencies(mlir-headers MLIRVCIXDialectEnumIncGen)
diff --git a/mlir/include/mlir/Dialect/VCIX/VCIX.td b/mlir/include/mlir/Dialect/VCIX/VCIX.td
new file mode 100644
index 00000000000000..2b5bbeb22e97fc
--- /dev/null
+++ b/mlir/include/mlir/Dialect/VCIX/VCIX.td
@@ -0,0 +1,305 @@
+//===-- VCIX.td - VCIX dialect operation definitions *- tablegen -*--------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// The file defines the basic operations for the VCIX dialect.
+//
+// The SiFive Vector Coprocessor Interface (VCIX) provides a flexible mechanism
+// to extend application processors with custom coprocessors and
+// variable-latency arithmetic units. The interface offers throughput comparable
+// to that of standard RISC-V vector instructions. To accelerate performance,
+// system designers may use VCIX as a low-latency, high-throughput interface to
+// a coprocessor
+//
+// https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
+//
+//===----------------------------------------------------------------------===//
+#ifndef VCIX
+#define VCIX
+
+include "mlir/IR/EnumAttr.td"
+include "mlir/IR/OpBase.td"
+include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
+include "mlir/Interfaces/SideEffectInterfaces.td"
+
+include "mlir/Dialect/VCIX/VCIXAttrs.td"
+
+//===----------------------------------------------------------------------===//
+// VCIX dialect definition.
+//===----------------------------------------------------------------------===//
+
+def VCIX_Dialect : Dialect {
+ let name = "vcix";
+ let cppNamespace = "::mlir::vcix";
+ let description = [{
+ The SiFive Vector Coprocessor Interface (VCIX) provides a flexible mechanism
+ to extend application processors with custom coprocessors and
+ variable-latency arithmetic units. The interface offers throughput comparable
+ to that of standard RISC-V vector instructions. To accelerate performance,
+ system designers may use VCIX as a low-latency, high-throughput interface to
+ a coprocessor
+
+ https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
+ }];
+
+ let usePropertiesForAttributes = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// VCIX Ops
+//===----------------------------------------------------------------------===//
+class VCIX_Op<string mnemonic, list<Trait> traits = []>
+ : Op<VCIX_Dialect, mnemonic, traits> {}
+
+class VCIX_IntrinOp<string mnemonic, list<Trait> traits = []>
+ : LLVM_OpBase<VCIX_Dialect, "intrin." #mnemonic, traits> {}
+
+//===----------------------------------------------------------------------===//
+// Unary VCIX operations
+//===----------------------------------------------------------------------===//
+def VCIX_UnaryROOp : VCIX_Op<"unary.ro", []> {
+ let summary = "Unary VCIX operation with side effects and without result";
+ let description = [{
+ Unary VCIX operation that has some side effects and does not produce result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.x 0000-- 1 ----- xs1 100 ----- none scalar xs1
+ sf.vc.i 0000-- 1 ----- simm 011 ----- none simm[4:0]
+ ```
+ }];
+
+ let arguments = (ins AnyTypeOf<[I<64>, I<32>, I<5>]>: $op,
+ RVLType: $rvl,
+ OpcodeIntAttr: $opcode,
+ VCIX_SewLmulAttr: $sew_lmul,
+ RAttr: $rs2,
+ RAttr: $rd);
+
+ let assemblyFormat = [{
+ $sew_lmul $op `,` $rvl attr-dict `:` `(` type($op) `,` type($rvl) `)`
+ }];
+
+ let hasVerifier = 1;
+}
+
+def VCIX_UnaryOp : VCIX_Op<"unary", []> {
+ let summary = "unary VCIX operation";
+ let description = [{
+ Unary VCIX operation that produces result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.v.x 0000-- 0 ----- xs1 100 vd vector vd scalar xs1
+ sf.vc.v.i 0000-- 0 ----- simm 011 vd vector vd simm[4:0]
+ ```
+ }];
+
+ let arguments = (ins AnyTypeOf<[I<64>, I<32>, I<5>]>: $op,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode,
+ RAttr: $rs2);
+
+ let results = (outs VectorOfRank1: $result);
+
+ let assemblyFormat = [{
+ $op (`,` $rvl^)? attr-dict
+ `:` `(` type($op) (`,` type($rvl)^)? `)` `->` type($result)
+ }];
+
+ let hasVerifier = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Binary VCIX operations
+//===----------------------------------------------------------------------===//
+def VCIX_BinaryROOp : VCIX_Op<"binary.ro", []> {
+ let summary = "Read-only binary VCIX operation";
+ let description = [{
+ Read-only binary VCIX operation that does not produce result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.v.vv 0010-- 1 vs2 vs1 000 ----- none vector vs1, vector vs2
+ sf.vc.v.xv 0010-- 1 vs2 xs1 100 ----- none scalar xs1, vector vs2
+ sf.vc.v.iv 0010-- 1 vs2 simm 011 ----- none simm[4:0], vector vs2
+ sf.vc.v.fv 0010-- 1 vs2 fs1 101 ----- none scalar fs1, vector vs2
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode,
+ RAttr: $rd);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) (`,` type($rvl)^)? `)`
+ }];
+
+ let hasVerifier = 1;
+}
+
+def VCIX_BinaryOp : VCIX_Op<"binary", []> {
+ let summary = "binary VCIX operation";
+ let description = [{
+ Binary VCIX operation that produces result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.v.vv 0010-- 0 vs2 vs1 000 vd vector vd vector vs1, vector vs2
+ sf.vc.v.xv 0010-- 0 vs2 xs1 100 vd vector vd scalar xs1, vector vs2
+ sf.vc.v.iv 0010-- 0 vs2 simm 011 vd vector vd simm[4:0], vector vs2
+ sf.vc.v.fv 0010-- 0 vs2 fs1 101 vd vector vd scalar fs1, vector vs2
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode);
+
+ let results = (outs VectorOfRank1: $result);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) (`,` type($rvl)^)? `)` `->` type($result)
+ }];
+
+ let hasVerifier = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Ternary VCIX operations
+//===----------------------------------------------------------------------===//
+def VCIX_TernaryROOp : VCIX_Op<"ternary.ro", []> {
+ let summary = "Ternary VCIX operation";
+ let description = [{
+ Ternary VCIX operation that does not generate result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.vvv 1010-- 1 vs2 vs1 000 vd none vector vs1, vector vs2, vector vd
+ sf.vc.xvv 1010-- 1 vs2 xs1 100 vd none scalar xs1, vector vs2, vector vd
+ sf.vc.ivv 1010-- 1 vs2 simm 011 vd none simm[4:0], vector vs2, vector vd
+ sf.vc.fvv 10101- 1 vs2 fs1 101 vd none scalar fs1, vector vs2, vector vd
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ VectorOfRank1: $op3,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 `,` $op3 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) `,` type($op3) (`,` type($rvl)^)? `)`
+ }];
+
+ let hasVerifier = 1;
+}
+
+def VCIX_TernaryOp : VCIX_Op<"ternary", []> {
+ let summary = "Ternary VCIX operation";
+ let description = [{
+ Ternary VCIX operation that produces result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.v.vvv 1010-- 0 vs2 vs1 000 vd vector vd vector vs1, vector vs2, vector vd
+ sf.vc.v.xvv 1010-- 0 vs2 xs1 100 vd vector vd scalar xs1, vector vs2, vector vd
+ sf.vc.v.ivv 1010-- 0 vs2 simm 011 vd vector vd simm[4:0], vector vs2, vector vd
+ sf.vc.v.fvv 10101- 0 vs2 fs1 101 vd vector vd scalar fs1, vector vs2, vector vd
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ VectorOfRank1: $op3,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode);
+
+ let results = (outs VectorOfRank1: $result);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 `,` $op3 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) `,` type($op3) (`,` type($rvl)^)? `)` `->` type($result)
+ }];
+
+ let hasVerifier = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Wide ternary VCIX operations
+//===----------------------------------------------------------------------===//
+def VCIX_WideTernaryROOp : VCIX_Op<"wide.ternary.ro", []> {
+ let summary = "Ternary VCIX operation";
+ let description = [{
+ Wide Ternary VCIX operation that does not produce result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.vvw 1111-- 1 vs2 vs1 000 vd none vector vs1, vector vs2, wide vd
+ sf.vc.xvw 1111-- 1 vs2 xs1 100 vd none scalar xs1, vector vs2, wide vd
+ sf.vc.ivw 1111-- 1 vs2 simm 011 vd none simm[4:0], vector vs2, wide vd
+ sf.vc.fvw 11111- 1 vs2 fs1 101 vd none scalar fs1, vector vs2, wide vd
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ VectorOfRank1: $op3,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 `,` $op3 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) `,` type($op3) (`,` type($rvl)^)? `)`
+ }];
+
+ let hasVerifier = 1;
+}
+
+def VCIX_WideTernaryOp : VCIX_Op<"wide.ternary", []> {
+ let summary = "Ternary VCIX operation";
+ let description = [{
+ Wide Ternary VCIX operation that produces result
+
+ Correponds to
+ ```
+ Mnemonic funct6 vm rs2 rs1 funct3 rd Destination Sources
+ sf.vc.v.vvw 1111-- 0 vs2 vs1 000 vd wide vd vector vs1, vector vs2, wide vd
+ sf.vc.v.xvw 1111-- 0 vs2 xs1 100 vd wide vd scalar xs1, vector vs2, wide vd
+ sf.vc.v.ivw 1111-- 0 vs2 simm 011 vd wide vd simm[4:0], vector vs2, wide vd
+ sf.vc.v.fvw 11111- 0 vs2 fs1 101 vd wide vd scalar fs1, vector vs2, wide vd
+ ```
+ }];
+
+ let arguments = (ins VectorOfRank1OrScalar: $op1,
+ VectorOfRank1: $op2,
+ VectorOfRank1: $op3,
+ Optional<RVLType>: $rvl,
+ OpcodeIntAttr: $opcode);
+
+ let results = (outs VectorOfRank1: $result);
+
+ let assemblyFormat = [{
+ $op1 `,` $op2 `,` $op3 (`,` $rvl^)? attr-dict `:`
+ `(` type($op1) `,` type($op2) `,` type($op3) (`,` type($rvl)^)? `)` `->` type($result)
+ }];
+
+ let hasVerifier = 1;
+}
+#endif // VCIX
diff --git a/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.h b/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.h
new file mode 100644
index 00000000000000..95b66ee2b9a924
--- /dev/null
+++ b/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.h
@@ -0,0 +1,20 @@
+//===- VCIXAttr.h - VCIX Dialect Attribute Definition -*- C++ -----------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_VCIX_TRANSFORMATTRS_H
+#define MLIR_DIALECT_VCIX_TRANSFORMATTRS_H
+
+#include "mlir/IR/Attributes.h"
+#include "mlir/IR/BuiltinAttributes.h"
+
+#include <cstdint>
+#include <optional>
+
+#include "mlir/Dialect/VCIX/VCIXDialectEnums.h.inc"
+
+#endif // MLIR_DIALECT_VCIX_TRANSFORMATTRS_H
diff --git a/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.td b/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.td
new file mode 100644
index 00000000000000..7f3ecc9a3f2d3c
--- /dev/null
+++ b/mlir/include/mlir/Dialect/VCIX/VCIXAttrs.td
@@ -0,0 +1,91 @@
+//===- VCIXAttrs.td - VCIX dialect attributes ----*- tablegen -----------*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#ifndef MLIR_DIALECT_VCIX_VCIXATTRS
+#define MLIR_DIALECT_VCIX_VCIXATTRS
+
+include "mlir/IR/EnumAttr.td"
+
+//===----------------------------------------------------------------------===//
+// VCIX helper type definitions
+//===----------------------------------------------------------------------===//
+def VectorOfRank1 : AnyTypeOf<[ScalableVectorOfRank<[1]>, VectorOfRank<[1]>]>;
+def VectorOfRank1OrScalar
+ : AnyTypeOf<[VectorOfRank1, I<64>, I<32>, F<16>, F<32>, F<64>, I<5>]>;
+def OpcodeI1Attr : AnyIntegerAttrBase<AnyI<1>, "1-bit integer attribute">;
+def OpcodeI2Attr : AnyIntegerAttrBase<AnyI<2>, "2-bit integer attribute">;
+def OpcodeIntAttr : AnyAttrOf<[OpcodeI1Attr, OpcodeI2Attr]>;
+def RAttr : AnyAttrOf<[AnyIntegerAttrBase<AnyI<5>, "5-bit integer attribute">]>;
+def RVLType : AnyTypeOf<[UI<64>, UI<32>]>;
+
+// Special version for intrinsic version where int attr is zext to i32 or i64
+// depending on xlen of the target
+def VectorOfRank1OrScalarIntrin
+ : AnyTypeOf<[VectorOfRank1, I<64>, I<32>, F<16>, F<32>, F<64>]>;
+def OpcodeIntrinIntAttr : AnyAttrOf<[I64Attr, I32Attr]>;
+def RIntrinAttr : AnyAttrOf<[I64Attr, I32Attr]>;
+def RVLIntrinType : AnyTypeOf<[I<64>, I<32>]>;
+
+def VCIX_e8mf8 : I32EnumAttrCase<"e8mf8", 0, "e8mf8">;
+def VCIX_e8mf4 : I32EnumAttrCase<"e8mf4", 1, "e8mf4">;
+def VCIX_e8mf2 : I32EnumAttrCase<"e8mf2", 2, "e8mf2">;
+def VCIX_e8m1 : I32EnumAttrCase<"e8m1", 3, "e8m1">;
+def VCIX_e8m2 : I32EnumAttrCase<"e8m2", 4, "e8m2">;
+def VCIX_e8m4 : I32EnumAttrCase<"e8m4", 5, "e8m4">;
+def VCIX_e8m8 : I32EnumAttrCase<"e8m8", 6, "e8m8">;
+
+def VCIX_e16mf4 : I32EnumAttrCase<"e16mf4", 7, "e16mf4">;
+def VCIX_e16mf2 : I32EnumAttrCase<"e16mf2", 8, "e16mf2">;
+def VCIX_e16m1 : I32EnumAttrCase<"e16m1", 9, "e16m1">;
+def VCIX_e16m2 : I32EnumAttrCase<"e16m2", 10, "e16m2">;
+def VCIX_e16m4 : I32EnumAttrCase<"e16m4", 11, "e16m4">;
+def VCIX_e16m8 : I32EnumAttrCase<"e16m8", 12, "e16m8">;
+
+def VCIX_e32mf2 : I32EnumAttrCase<"e32mf2", 13, "e32mf2">;
+def VCIX_e32m1 : I32EnumAttrCase<"e32m1", 14, "e32m1">;
+def VCIX_e32m2 : I32EnumAttrCase<"e32m2", 15, "e32m2">;
+def VCIX_e32m4 : I32EnumAttrCase<"e32m4", 16, "e32m4">;
+def VCIX_e32m8 : I32EnumAttrCase<"e32m8", 17, "e32m8">;
+
+def VCIX_e64m1 : I32EnumAttrCase<"e64m1", 18, "e64m1">;
+def VCIX_e64m2 : I32EnumAttrCase<"e64m2", 19, "e64m2">;
+def VCIX_e64m4 : I32EnumAttrCase<"e64m4", 20, "e64m4">;
+def VCIX_e64m8 : I32EnumAttrCase<"e64m8", 21, "e64m8">;
+
+def VCIX_SewLmulAttr : I32EnumAttr<"SewLmul",
+ "A list of all possible SEW and LMUL",
+ [
+ VCIX_e8mf8,
+ VCIX_e8mf4,
+ VCIX_e8mf2,
+ VCIX_e8m1,
+ VCIX_e8m2,
+ VCIX_e8m4,
+ VCIX_e8m8,
+
+ VCIX_e16mf4,
+ VCIX_e16mf2,
+ VCIX_e16m1,
+ VCIX_e16m2,
+ VCIX_e16m4,
+ VCIX_e16m8,
+
+ VCIX_e32mf2,
+ VCIX_e32m1,
+ VCIX_e32m2,
+ VCIX_e32m4,
+ VCIX_e32m8,
+
+ VCIX_e64m1,
+ VCIX_e64m2,
+ VCIX_e64m4,
+ VCIX_e64m8,
+ ]> {
+ let cppNamespace = "::mlir::vcix";
+}
+
+#endif // MLIR_DIALECT_VCIX_VCIXATTRS
diff --git a/mlir/include/mlir/Dialect/VCIX/VCIXDialect.h b/mlir/include/mlir/Dialect/VCIX/VCIXDialect.h
new file mode 100644
index 00000000000000..0e795f42f58dee
--- /dev/null
+++ b/mlir/include/mlir/Dialect/VCIX/VCIXDialect.h
@@ -0,0 +1,28 @@
+//===- VCIXDialect.h - MLIR Dialect for VCIX --------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Target dialect for VCIX in MLIR.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_VCIX_VCIXDIALECT_H_
+#define MLIR_DIALECT_VCIX_VCIXDIALECT_H_
+
+#include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/IR/BuiltinTypes.h"
+#include "mlir/IR/Dialect.h"
+#include "mlir/IR/OpDefinition.h"
+#include "mlir/Interfaces/SideEffectInterfaces.h"
+
+#include "mlir/Dialect/VCIX/VCIXAttrs.h"
+#include "mlir/Dialect/VCIX/VCIXDialect.h.inc"
+
+#define GET_OP_CLASSES
+#include "mlir/Dialect/VCIX/VCIX.h.inc"
+
+#endif // MLIR_DIALECT_VCIX_VCIXDIALECT_H_
diff --git a/mlir/include/mlir/InitAllDialects.h b/mlir/include/mlir/InitAllDialects.h
index 19a62cadaa2e04..3dcb4a41e9d17c 100644
--- a/mlir/include/mlir/InitAllDialects.h
+++ b/mlir/include/mlir/InitAllDialects.h
@@ -83,6 +83,7 @@
#include "mlir/Dialect/Tr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/74780
More information about the Mlir-commits
mailing list