[Mlir-commits] [mlir] 8f9aac4 - [mlir][vector] Fix invalid IR in `vector.print` lowering (#74410)

[llvmlistbot at llvm.org]

Author: Matthias Springer
Date: 2023-12-06T09:44:03+09:00
New Revision: 8f9aac44279dbc1e7fdc5e4263da2b237db0cfc1

URL: https://github.com/llvm/llvm-project/commit/8f9aac44279dbc1e7fdc5e4263da2b237db0cfc1
DIFF: https://github.com/llvm/llvm-project/commit/8f9aac44279dbc1e7fdc5e4263da2b237db0cfc1.diff

LOG: [mlir][vector] Fix invalid IR in `vector.print` lowering (#74410)

`DecomposePrintOpConversion` used to generate invalid op such as:
```
error: 'arith.extsi' op operand type 'vector<10xi32>' and result type 'vector<10xi32>' are cast incompatible
  vector.print %v9 : vector<10xi32>
```

This commit fixes tests such as
`mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i32.mlir` when
verifying the IR after each pattern application (#74270).

Added: 
    

Modified: 
    mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
index 33a77d7576ba7..2ee314e9fedfe 100644
--- a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
+++ b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
@@ -726,12 +726,14 @@ struct DecomposePrintOpConversion : public VectorToSCFPattern<vector::PrintOp> {
       auto targetVectorType = vectorType.cloneWith({}, legalIntTy);
       value = rewriter.create<vector::BitCastOp>(loc, signlessSourceVectorType,
                                                  value);
-      if (width == 1 || intTy.isUnsigned())
-        value = rewriter.create<arith::ExtUIOp>(loc, signlessTargetVectorType,
-                                                value);
-      else
-        value = rewriter.create<arith::ExtSIOp>(loc, signlessTargetVectorType,
-                                                value);
+      if (value.getType() != signlessTargetVectorType) {
+        if (width == 1 || intTy.isUnsigned())
+          value = rewriter.create<arith::ExtUIOp>(loc, signlessTargetVectorType,
+                                                  value);
+        else
+          value = rewriter.create<arith::ExtSIOp>(loc, signlessTargetVectorType,
+                                                  value);
+      }
       value = rewriter.create<vector::BitCastOp>(loc, targetVectorType, value);
       vectorType = targetVectorType;
     }