[Mlir-commits] [mlir] [mlir][nvvm] Introduce `nvvm.fence.proxy` (PR #74057)

[llvmlistbot at llvm.org]

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@@ -428,6 +428,13 @@ def ProxyKindAttr : EnumAttr<NVVM_Dialect, ProxyKind, "proxy_kind"> {
 def NVVM_FenceProxyOp : NVVM_PTXBuilder_Op<"fence.proxy">,
   Arguments<(ins ProxyKindAttr:$kind,
                  OptionalAttr<SharedSpaceAttr>:$space)> {
+  let description = [{
+    Fence operation with proxy to establish an ordering between memory accesses
+    that may happen through different proxies.
+    [For more information, see PTX ISA]
+    (https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar)
+  }];
+  
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durga4github wrote:

thanks for adding this!

https://github.com/llvm/llvm-project/pull/74057