[Mlir-commits] [mlir] 8a21dfe - [mlir][openacc] Accept acc.serial has parent of acc.yield op

[Valentin Clement]

Author: Valentin Clement
Date: 2023-04-13T14:35:22-07:00
New Revision: 8a21dfe1bd9fa18651676062dfe17feb71fe2344

URL: https://github.com/llvm/llvm-project/commit/8a21dfe1bd9fa18651676062dfe17feb71fe2344
DIFF: https://github.com/llvm/llvm-project/commit/8a21dfe1bd9fa18651676062dfe17feb71fe2344.diff

LOG: [mlir][openacc] Accept acc.serial has parent of acc.yield op

acc.serial op is modeled on the acc.parallel op.
acc.yield operation must then accept acc.serial has a parent
operation.

Reviewed By: PeteSteinfeld, razvanlupusoru

Differential Revision: https://reviews.llvm.org/D148258

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
    mlir/test/Dialect/OpenACC/ops.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
index f0f0acc39cb6a..2bc4267972e37 100644
--- a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+++ b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
@@ -497,7 +497,7 @@ def OpenACC_LoopOp : OpenACC_Op<"loop", [AttrSizedOperandSegments]> {
 
 // Yield operation for the acc.loop and acc.parallel operations.
 def OpenACC_YieldOp : OpenACC_Op<"yield", [Terminator,
-    ParentOneOf<["ParallelOp, LoopOp"]>]> {
+    ParentOneOf<["ParallelOp, LoopOp, SerialOp"]>]> {
   let summary = "Acc yield and termination operation";
 
   let description = [{

diff  --git a/mlir/test/Dialect/OpenACC/ops.mlir b/mlir/test/Dialect/OpenACC/ops.mlir
index c659467626426..be014fd374ef3 100644
--- a/mlir/test/Dialect/OpenACC/ops.mlir
+++ b/mlir/test/Dialect/OpenACC/ops.mlir
@@ -530,6 +530,9 @@ func.func @testserialop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10
   } attributes {waitAttr}
   acc.serial {
   } attributes {selfAttr}
+  acc.serial {
+    acc.yield
+  } attributes {selfAttr}
   return
 }
 
@@ -577,6 +580,9 @@ func.func @testserialop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10
 // CHECK-NEXT: } attributes {waitAttr}
 // CHECK:      acc.serial {
 // CHECK-NEXT: } attributes {selfAttr}
+// CHECK:      acc.serial {
+// CHECK:        acc.yield
+// CHECK-NEXT: } attributes {selfAttr}
 
 // -----