[Mlir-commits] [mlir] d7c5391 - [mlir][sparse] fix python indentation in test

Aart Bik llvmlistbot at llvm.org
Wed Sep 7 10:05:43 PDT 2022


Author: Aart Bik
Date: 2022-09-07T10:05:32-07:00
New Revision: d7c53912d27aebbba9b798975aaa8789f9cf3c94

URL: https://github.com/llvm/llvm-project/commit/d7c53912d27aebbba9b798975aaa8789f9cf3c94
DIFF: https://github.com/llvm/llvm-project/commit/d7c53912d27aebbba9b798975aaa8789f9cf3c94.diff

LOG: [mlir][sparse] fix python indentation in test

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D133385

Added: 
    

Modified: 
    mlir/test/Integration/Dialect/SparseTensor/python/test_SDDMM.py

Removed: 
    


################################################################################
diff  --git a/mlir/test/Integration/Dialect/SparseTensor/python/test_SDDMM.py b/mlir/test/Integration/Dialect/SparseTensor/python/test_SDDMM.py
index 4a612c95655bf..fc215614c32f2 100644
--- a/mlir/test/Integration/Dialect/SparseTensor/python/test_SDDMM.py
+++ b/mlir/test/Integration/Dialect/SparseTensor/python/test_SDDMM.py
@@ -146,16 +146,16 @@ def main():
         for pwidth in [32]:
           for iwidth in [32]:
             for vec in vec_strategy:
-                for e in [True]:
-                  vl = 1 if vec == 0 else 16
-                  attr = st.EncodingAttr.get(level, ordering, pwidth, iwidth)
-                  opt = (f'parallelization-strategy=none '
-                         f'vectorization-strategy={vec} '
-                         f'vl={vl} enable-simd-index32={e}')
-                  compiler = sparse_compiler.SparseCompiler(
-                      options=opt, opt_level=0, shared_libs=[support_lib])
-                  build_compile_and_run_SDDMMM(attr, compiler)
-                  count = count + 1
+              for e in [True]:
+                vl = 1 if vec == 0 else 16
+                attr = st.EncodingAttr.get(level, ordering, pwidth, iwidth)
+                opt = (f'parallelization-strategy=none '
+                       f'vectorization-strategy={vec} '
+                       f'vl={vl} enable-simd-index32={e}')
+                compiler = sparse_compiler.SparseCompiler(
+                    options=opt, opt_level=0, shared_libs=[support_lib])
+                build_compile_and_run_SDDMMM(attr, compiler)
+                count = count + 1
   # CHECK: Passed 16 tests
   print('Passed ', count, 'tests')
 


        


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