[Mlir-commits] [mlir] ea9cae0 - [mlir][llvm] Use tablegen to import shufflevector from LLVM IR.
Tobias Gysi
llvmlistbot at llvm.org
Fri Oct 14 04:59:14 PDT 2022
Author: Tobias Gysi
Date: 2022-10-14T14:46:05+03:00
New Revision: ea9cae03d780de4cc84d4777445ad8de89ebf361
URL: https://github.com/llvm/llvm-project/commit/ea9cae03d780de4cc84d4777445ad8de89ebf361
DIFF: https://github.com/llvm/llvm-project/commit/ea9cae03d780de4cc84d4777445ad8de89ebf361.diff
LOG: [mlir][llvm] Use tablegen to import shufflevector from LLVM IR.
The revision imports the shuffle vector operation using
tablegen generated builders. Additionally, it moves its test to
the instructions.ll test file.
Depends on D135874
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D135880
Added:
Modified:
mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
mlir/test/Target/LLVMIR/Import/basic.ll
mlir/test/Target/LLVMIR/Import/instructions.ll
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
index c87be7c5863e9..68d59cb3817b8 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
@@ -914,9 +914,16 @@ def LLVM_ShuffleVectorOp : LLVM_Op<"shufflevector",
let hasVerifier = 1;
+ string llvmInstName = "ShuffleVector";
string llvmBuilder = [{
$res = builder.CreateShuffleVector($v1, $v2, $mask);
}];
+ string mlirBuilder = [{
+ auto *svInst = cast<llvm::ShuffleVectorInst>(inst);
+ SmallVector<int32_t> mask(svInst->getShuffleMask());
+ $res = $_builder.create<LLVM::ShuffleVectorOp>(
+ $_location, $v1, $v2, mask);
+ }];
}
// Misc operations.
diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
index 3f95afb19353b..163281e390a56 100644
--- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -993,16 +993,6 @@ LogicalResult Importer::processInstruction(llvm::Instruction *inst) {
mapValue(inst, res);
return success();
}
- if (inst->getOpcode() == llvm::Instruction::ShuffleVector) {
- auto *svInst = cast<llvm::ShuffleVectorInst>(inst);
- Value vec1 = processValue(svInst->getOperand(0));
- Value vec2 = processValue(svInst->getOperand(1));
-
- SmallVector<int32_t> mask(svInst->getShuffleMask());
- Value res = b.create<ShuffleVectorOp>(loc, vec1, vec2, mask);
- mapValue(inst, res);
- return success();
- }
return emitError(loc) << "unknown instruction: " << diag(*inst);
}
diff --git a/mlir/test/Target/LLVMIR/Import/basic.ll b/mlir/test/Target/LLVMIR/Import/basic.ll
index 6751e4132800e..65c521097998d 100644
--- a/mlir/test/Target/LLVMIR/Import/basic.ll
+++ b/mlir/test/Target/LLVMIR/Import/basic.ll
@@ -448,18 +448,6 @@ def: ; pred: bb3, bbs
ret void
}
-; Shufflevector
-; CHECK-LABEL: llvm.func @shuffle_vec
-define <4 x half> @shuffle_vec(<4 x half>* %arg0, <4 x half>* %arg1) {
- ; CHECK: %[[V0:.+]] = llvm.load %{{.+}} : !llvm.ptr<vector<4xf16>>
- %val0 = load <4 x half>, <4 x half>* %arg0
- ; CHECK: %[[V1:.+]] = llvm.load %{{.+}} : !llvm.ptr<vector<4xf16>>
- %val1 = load <4 x half>, <4 x half>* %arg1
- ; CHECK: llvm.shufflevector %[[V0]], %[[V1]] [2, 3, -1, -1] : vector<4xf16>
- %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
- ret <4 x half> %shuffle
-}
-
; Varadic function definition
%struct.va_list = type { i8* }
diff --git a/mlir/test/Target/LLVMIR/Import/instructions.ll b/mlir/test/Target/LLVMIR/Import/instructions.ll
index b127586ddfe5c..1836f88e7e4a5 100644
--- a/mlir/test/Target/LLVMIR/Import/instructions.ll
+++ b/mlir/test/Target/LLVMIR/Import/instructions.ll
@@ -323,6 +323,17 @@ define void @select(i32 %arg0, i32 %arg1, i1 %cond) {
; // -----
+; CHECK-LABEL: func @shuffle_vec
+; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
+; CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]
+define <4 x half> @shuffle_vec(<4 x half> %arg1, <4 x half> %arg2) {
+ ; CHECK: llvm.shufflevector %[[ARG1]], %[[ARG2]] [2, 3, -1, -1] : vector<4xf16>
+ %1 = shufflevector <4 x half> %arg1, <4 x half> %arg2, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+ ret <4 x half> %1
+}
+
+; // -----
+
; CHECK-LABEL: @alloca
; CHECK-SAME: %[[SIZE:[a-zA-Z0-9]+]]
define double* @alloca(i64 %size) {
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