[Mlir-commits] [mlir] 7b0e041 - [mlir][spirv] Add AssumeTrueKHROp

[Ivan Butygin]

Author: Ivan Butygin
Date: 2022-03-15T13:03:45+03:00
New Revision: 7b0e041df8c02c8fc839447588c1e9181e80943e

URL: https://github.com/llvm/llvm-project/commit/7b0e041df8c02c8fc839447588c1e9181e80943e
DIFF: https://github.com/llvm/llvm-project/commit/7b0e041df8c02c8fc839447588c1e9181e80943e.diff

LOG: [mlir][spirv] Add AssumeTrueKHROp

Differential Revision: https://reviews.llvm.org/D121601

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
    mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
    mlir/test/Dialect/SPIRV/IR/misc-ops.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index c342331873b37..c729b18d8ac8e 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -4174,6 +4174,7 @@ def SPV_OC_OpCooperativeMatrixMulAddNV : I32EnumAttrCase<"OpCooperativeMatrixMul
 def SPV_OC_OpCooperativeMatrixLengthNV : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
 def SPV_OC_OpSubgroupBlockReadINTEL    : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
 def SPV_OC_OpSubgroupBlockWriteINTEL   : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
+def SPV_OC_OpAssumeTrueKHR             : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
 def SPV_OC_OpAtomicFAddEXT             : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
 
 def SPV_OpcodeAttr :
@@ -4240,7 +4241,7 @@ def SPV_OpcodeAttr :
       SPV_OC_OpCooperativeMatrixLoadNV, SPV_OC_OpCooperativeMatrixStoreNV,
       SPV_OC_OpCooperativeMatrixMulAddNV, SPV_OC_OpCooperativeMatrixLengthNV,
       SPV_OC_OpSubgroupBlockReadINTEL, SPV_OC_OpSubgroupBlockWriteINTEL,
-      SPV_OC_OpAtomicFAddEXT
+      SPV_OC_OpAssumeTrueKHR, SPV_OC_OpAtomicFAddEXT
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!

diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
index 7b4f7a24d9bd7..956d39a16d645 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
@@ -18,6 +18,44 @@ include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 // -----
 
+def SPV_AssumeTrueKHROp : SPV_Op<"AssumeTrueKHR", []> {
+  let summary = "TBD";
+
+  let description = [{
+
+
+    <!-- End of AutoGen section -->
+
+    ```
+    assumetruekhr-op ::= `spv.AssumeTrueKHR` ssa-use
+    ```mlir
+
+    #### Example:
+
+    ```
+    spv.AssumeTrueKHR %arg
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPV_V_1_0>,
+    MaxVersion<SPV_V_1_5>,
+    Extension<[SPV_KHR_expect_assume]>,
+    Capability<[SPV_C_ExpectAssumeKHR]>
+  ];
+
+  let arguments = (ins
+    SPV_Bool:$condition
+  );
+
+  let results = (outs);
+
+  let hasVerifier = 0;
+  let assemblyFormat = "$condition attr-dict";
+}
+
+// -----
+
 def SPV_UndefOp : SPV_Op<"Undef", []> {
   let summary = "Make an intermediate object whose value is undefined.";
 

diff  --git a/mlir/test/Dialect/SPIRV/IR/misc-ops.mlir b/mlir/test/Dialect/SPIRV/IR/misc-ops.mlir
index 3a6006d542daf..171c0f5586e80 100644
--- a/mlir/test/Dialect/SPIRV/IR/misc-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/misc-ops.mlir
@@ -27,3 +27,20 @@ func @undef() -> () {
   %0 = spv.Undef
   spv.Return
 }
+
+// -----
+
+func @assume_true(%arg : i1) -> () {
+  // CHECK: spv.AssumeTrueKHR %{{.*}}
+  spv.AssumeTrueKHR %arg
+  spv.Return
+}
+
+// -----
+
+func @assume_true(%arg : f32) -> () {
+  // expected-error @+2{{use of value '%arg' expects 
diff erent type than prior uses: 'i1' vs 'f32'}}
+  // expected-note @-2 {{prior use here}}
+  spv.AssumeTrueKHR %arg
+  spv.Return
+}