[Mlir-commits] [mlir] eb27da7 - [mlir] Ignore index data layout in translation to LLVM

[Alex Zinenko]

Author: Alex Zinenko
Date: 2022-03-02T16:56:21+01:00
New Revision: eb27da7dec67f1a36505b589b786ba1a499c274a

URL: https://github.com/llvm/llvm-project/commit/eb27da7dec67f1a36505b589b786ba1a499c274a
DIFF: https://github.com/llvm/llvm-project/commit/eb27da7dec67f1a36505b589b786ba1a499c274a.diff

LOG: [mlir] Ignore index data layout in translation to LLVM

It can be present, but is irrelevant for the translation.

Added: 
    

Modified: 
    mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
    mlir/test/Target/LLVMIR/data-layout.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
index c75b1cdf5446a..e16066679bc71 100644
--- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
@@ -86,6 +86,9 @@ translateDataLayout(DataLayoutSpecInterface attribute,
     auto type = entry.getKey().dyn_cast<Type>();
     if (!type)
       continue;
+    // Data layout for the index type is irrelevant at this point.
+    if (type.isa<IndexType>())
+      continue;
     FailureOr<std::string> prefix =
         llvm::TypeSwitch<Type, FailureOr<std::string>>(type)
             .Case<IntegerType>(

diff  --git a/mlir/test/Target/LLVMIR/data-layout.mlir b/mlir/test/Target/LLVMIR/data-layout.mlir
index 11fb2787adc9f..ba8960f38b8d2 100644
--- a/mlir/test/Target/LLVMIR/data-layout.mlir
+++ b/mlir/test/Target/LLVMIR/data-layout.mlir
@@ -6,6 +6,7 @@
 // CHECK: f80:128:256
 module attributes {dlti.dl_spec = #dlti.dl_spec<
 #dlti.dl_entry<"dlti.endianness", "big">,
+#dlti.dl_entry<index, 64>,
 #dlti.dl_entry<i64, dense<[64,128]> : vector<2xi32>>,
 #dlti.dl_entry<f80, dense<[128,256]> : vector<2xi32>>
 >} {