[Mlir-commits] [mlir] b2671d8 - [mlir][spirv] Fix bitcast input order for UnifyAliasedResourcePass

[Lei Zhang]

Author: Lei Zhang
Date: 2022-06-23T22:19:08-04:00
New Revision: b2671d8898e9f5aa66930ed17f9a3f108c6a9ab4

URL: https://github.com/llvm/llvm-project/commit/b2671d8898e9f5aa66930ed17f9a3f108c6a9ab4
DIFF: https://github.com/llvm/llvm-project/commit/b2671d8898e9f5aa66930ed17f9a3f108c6a9ab4.diff

LOG: [mlir][spirv] Fix bitcast input order for UnifyAliasedResourcePass

spv.bitcast from a vector to a scalar expects the lower-numbered
components of the the vector to map to the lower-ordered bits of
the scalar. That actually already matches how little endian stores
data in the memory. So we just need to read and push to the back
of the vector sequentially.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D128473

Added: 
    

Modified: 
    mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
    mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp b/mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
index 2dc4d737a71c..e95a4cc395ce 100644
--- a/mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
+++ b/mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
@@ -455,12 +455,14 @@ struct ConvertLoad : public ConvertAliasResource<spirv::LoadOp> {
                                                       indices.back(), oneValue);
       auto componentAcOp =
           rewriter.create<spirv::AccessChainOp>(loc, acOp.base_ptr(), indices);
+      // Assuming little endian, this reads lower-ordered bits of the number to
+      // lower-numbered components of the vector.
       components.push_back(rewriter.create<spirv::LoadOp>(loc, componentAcOp));
     }
-    std::reverse(components.begin(), components.end()); // For little endian..
 
     // Create a vector of the components and then cast back to the larger
-    // bitwidth element type.
+    // bitwidth element type. For spv.bitcast, the lower-numbered components of
+    // the vector map to lower-ordered bits of the larger bitwidth element type.
     auto vectorType = VectorType::get({ratio}, dstElemType);
     Value vectorValue = rewriter.create<spirv::CompositeConstructOp>(
         loc, vectorType, components);

diff  --git a/mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir b/mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
index 0b36178783f0..1d0c81d72366 100644
--- a/mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
+++ b/mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
@@ -251,7 +251,7 @@ spv.module Logical GLSL450 {
 //     CHECK:   %[[AC1:.+]] = spv.AccessChain %[[ADDR]][%[[ZERO]], %[[ADD]]]
 //     CHECK:   %[[LOAD1:.+]] = spv.Load "StorageBuffer" %[[AC1]] : f32
 
-//     CHECK:   %[[CC:.+]] = spv.CompositeConstruct %[[LOAD1]], %[[LOAD0]]
+//     CHECK:   %[[CC:.+]] = spv.CompositeConstruct %[[LOAD0]], %[[LOAD1]]
 //     CHECK:   %[[CAST:.+]] = spv.Bitcast %[[CC]] : vector<2xf32> to i64
 //     CHECK:   spv.ReturnValue %[[CAST]]