[Mlir-commits] [mlir] fe23a6f - [mlir] Fixup python bindings after splitting cf ops from std.

[River Riddle]

Author: Stella Laurenzo
Date: 2022-02-06T14:51:17-08:00
New Revision: fe23a6fb75e6ec7f2b51fb90d45ac684cc641665

URL: https://github.com/llvm/llvm-project/commit/fe23a6fb75e6ec7f2b51fb90d45ac684cc641665
DIFF: https://github.com/llvm/llvm-project/commit/fe23a6fb75e6ec7f2b51fb90d45ac684cc641665.diff

LOG: [mlir] Fixup python bindings after splitting cf ops from std.

Added: 
    mlir/python/mlir/dialects/ControlFlowOps.td
    mlir/python/mlir/dialects/cf.py

Modified: 
    mlir/python/CMakeLists.txt
    mlir/test/python/ir/blocks.py

Removed: 
    


################################################################################
diff  --git a/mlir/python/CMakeLists.txt b/mlir/python/CMakeLists.txt
index 59ddd83fb8b0f..bf379e9b2ec8c 100644
--- a/mlir/python/CMakeLists.txt
+++ b/mlir/python/CMakeLists.txt
@@ -72,6 +72,14 @@ declare_mlir_dialect_python_bindings(
     dialects/_builtin_ops_ext.py
   DIALECT_NAME builtin)
 
+declare_mlir_dialect_python_bindings(
+  ADD_TO_PARENT MLIRPythonSources.Dialects
+  ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir"
+  TD_FILE dialects/ControlFlowOps.td
+  SOURCES
+    dialects/cf.py
+  DIALECT_NAME cf)
+
 declare_mlir_dialect_python_bindings(
   ADD_TO_PARENT MLIRPythonSources.Dialects
   ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir"

diff  --git a/mlir/python/mlir/dialects/ControlFlowOps.td b/mlir/python/mlir/dialects/ControlFlowOps.td
new file mode 100644
index 0000000000000..1bb4d41f2626b
--- /dev/null
+++ b/mlir/python/mlir/dialects/ControlFlowOps.td
@@ -0,0 +1,15 @@
+//===-- ControlFlowOps.td - Python ControlFlowOps bindings -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#ifndef PYTHON_BINDINGS_CONTROL_FLOW_OPS
+#define PYTHON_BINDINGS_CONTROL_FLOW_OPS
+
+include "mlir/Bindings/Python/Attributes.td"
+include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.td"
+
+#endif

diff  --git a/mlir/python/mlir/dialects/cf.py b/mlir/python/mlir/dialects/cf.py
new file mode 100644
index 0000000000000..c2e357a8e6565
--- /dev/null
+++ b/mlir/python/mlir/dialects/cf.py
@@ -0,0 +1,5 @@
+#  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+#  See https://llvm.org/LICENSE.txt for license information.
+#  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+from ._cf_ops_gen import *

diff  --git a/mlir/test/python/ir/blocks.py b/mlir/test/python/ir/blocks.py
index 811dcd7c2bdd4..5aa1bf82de779 100644
--- a/mlir/test/python/ir/blocks.py
+++ b/mlir/test/python/ir/blocks.py
@@ -5,6 +5,7 @@
 import itertools
 from mlir.ir import *
 from mlir.dialects import builtin
+from mlir.dialects import cf
 # Note: std dialect needed for terminators.
 from mlir.dialects import std
 
@@ -43,11 +44,11 @@ def testBlockCreation():
 
       with InsertionPoint(entry_block) as entry_ip:
         assert entry_ip.block == entry_block
-        std.BranchOp([i16_arg], dest=middle_block)
+        cf.BranchOp([i16_arg], dest=middle_block)
 
       with InsertionPoint(middle_block) as middle_ip:
         assert middle_ip.block == middle_block
-        std.BranchOp([i32_arg], dest=successor_block)
+        cf.BranchOp([i32_arg], dest=successor_block)
     print(module.operation)
     # Ensure region back references are coherent.
     assert entry_block.region == middle_block.region == successor_block.region