[Mlir-commits] [mlir] c03fe1e - [mlir][spirv] Add StreamingInterfaceINTEL to SPIRVBase.td

[Lei Zhang]

Author: Mark Mendell
Date: 2022-12-22T10:28:02-08:00
New Revision: c03fe1ebbd8e45a8902b2b5484e203192f7b125c

URL: https://github.com/llvm/llvm-project/commit/c03fe1ebbd8e45a8902b2b5484e203192f7b125c
DIFF: https://github.com/llvm/llvm-project/commit/c03fe1ebbd8e45a8902b2b5484e203192f7b125c.diff

LOG: [mlir][spirv] Add StreamingInterfaceINTEL to SPIRVBase.td

StreamingInterfaceINTEL has been recently added to the SPIR-V headers:
https://github.com/KhronosGroup/SPIRV-Headers/commit/70ff9d939cd7fd0c758756ac57ab0c7c6d6c64d6

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D140476

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index 795a39856cd21..7ca32d92c583a 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -3098,6 +3098,11 @@ def SPIRV_EM_SchedulerTargetFmaxMhzINTEL      : I32EnumAttrCase<"SchedulerTarget
     Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
   ];
 }
+def SPIRV_EM_StreamingInterfaceINTEL          : I32EnumAttrCase<"StreamingInterfaceINTEL", 6154> {
+  list<Availability> availability = [
+    Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
+  ];
+}
 def SPIRV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
   list<Availability> availability = [
     Capability<[SPIRV_C_VectorComputeINTEL]>
@@ -3135,7 +3140,8 @@ def SPIRV_ExecutionModeAttr :
       SPIRV_EM_FloatingPointModeALTINTEL, SPIRV_EM_FloatingPointModeIEEEINTEL,
       SPIRV_EM_MaxWorkgroupSizeINTEL, SPIRV_EM_MaxWorkDimINTEL,
       SPIRV_EM_NoGlobalOffsetINTEL, SPIRV_EM_NumSIMDWorkitemsINTEL,
-      SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_NamedBarrierCountINTEL
+      SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_StreamingInterfaceINTEL,
+      SPIRV_EM_NamedBarrierCountINTEL
     ]>;
 
 def SPIRV_EM_Vertex                 : I32EnumAttrCase<"Vertex", 0> {