[Mlir-commits] [mlir] 3a72906 - [IR] Update llvm.prefetch to match docs

Archibald Elliott llvmlistbot at llvm.org
Fri Aug 19 01:12:11 PDT 2022


Author: Archibald Elliott
Date: 2022-08-19T09:11:17+01:00
New Revision: 3a729069e463440035284ae6a27798b2573223de

URL: https://github.com/llvm/llvm-project/commit/3a729069e463440035284ae6a27798b2573223de
DIFF: https://github.com/llvm/llvm-project/commit/3a729069e463440035284ae6a27798b2573223de.diff

LOG: [IR] Update llvm.prefetch to match docs

The current llvm.prefetch intrinsic docs state "The rw, locality and
cache type arguments must be constant integers."

This change:
- Makes arg 3 (cache type) an ImmArg
- Improves the verifier error messages to reference the incorrect
  argument.
- Fixes two tests which contradict the docs.

This is needed as the lowering to GlobalISel is different for ImmArgs
compared to other constants. The non-ImmArgs create a G_CONSTANT MIR
instruction, the for ImmArgs the constant is put directly on the
intrinsic's MIR instruction as an immediate.

Differential Revision: https://reviews.llvm.org/D132042

Added: 
    

Modified: 
    llvm/include/llvm/IR/Intrinsics.td
    llvm/lib/IR/Verifier.cpp
    llvm/test/Assembler/auto_upgrade_intrinsics.ll
    llvm/test/CodeGen/RISCV/prefetch.ll
    mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 8a04c495edb11..32f0560005838 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -567,7 +567,7 @@ def int_prefetch
     : DefaultAttrsIntrinsic<[], [ llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ],
                 [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
                  ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
-                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
+                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
 def int_pcmarker      : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>;
 
 def int_readcyclecounter : DefaultAttrsIntrinsic<[llvm_i64_ty]>;

diff  --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index f8cf0ef798209..693757d90a1d4 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -5121,9 +5121,12 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
           Call);
     break;
   case Intrinsic::prefetch:
-    Check(cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue() < 2 &&
-              cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
-          "invalid arguments to llvm.prefetch", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue() < 2,
+          "rw argument to llvm.prefetch must be 0-1", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
+          "locality argument to llvm.prefetch must be 0-4", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(3))->getZExtValue() < 2,
+          "cache type argument to llvm.prefetch must be 0-1", Call);
     break;
   case Intrinsic::stackprotector:
     Check(isa<AllocaInst>(Call.getArgOperand(1)->stripPointerCasts()),

diff  --git a/llvm/test/Assembler/auto_upgrade_intrinsics.ll b/llvm/test/Assembler/auto_upgrade_intrinsics.ll
index 4758c7e134806..914de9a77fe32 100644
--- a/llvm/test/Assembler/auto_upgrade_intrinsics.ll
+++ b/llvm/test/Assembler/auto_upgrade_intrinsics.ll
@@ -189,24 +189,24 @@ define void @tests.lifetime.start.end.unnamed() {
 declare void @llvm.prefetch(i8*, i32, i32, i32)
 define void @test.prefetch(i8* %ptr) {
 ; CHECK-LABEL: @test.prefetch(
-; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 
 declare void @llvm.prefetch.p0i8(i8*, i32, i32, i32)
 define void @test.prefetch.2(i8* %ptr) {
 ; CHECK-LABEL: @test.prefetch.2(
-; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 
 declare void @llvm.prefetch.unnamed(%0**, i32, i32, i32)
 define void @test.prefetch.unnamed(%0** %ptr) {
 ; CHECK-LABEL: @test.prefetch.unnamed(
-; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 

diff  --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index 7891b2e8c7498..be9cb5e6327bc 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -14,6 +14,6 @@ define void @test_prefetch(i8* %a) nounwind {
 ; RV64I-LABEL: test_prefetch:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
-  call void @llvm.prefetch(i8* %a, i32 0, i32 1, i32 2)
+  call void @llvm.prefetch(i8* %a, i32 0, i32 2, i32 1)
   ret void
 }

diff  --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
index 752f5a30e3ef2..c87ff8551002b 100644
--- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -712,7 +712,7 @@ llvm.func @vector_insert_extract(%f256: vector<8xi32>, %f128: vector<4xi32>,
 // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
 // CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float)
 // CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
-// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32)
+// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32 immarg)
 // CHECK-DAG: declare float @llvm.exp.f32(float)
 // CHECK-DAG: declare <8 x float> @llvm.exp.v8f32(<8 x float>) #0
 // CHECK-DAG: declare float @llvm.log.f32(float)


        


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