[Mlir-commits] [mlir] 4bd25d0 - [mlir][spirv] Refresh base definitions to latest spec (v1.6)
Lei Zhang
llvmlistbot at llvm.org
Mon Aug 8 09:23:01 PDT 2022
Author: Lei Zhang
Date: 2022-08-08T12:22:32-04:00
New Revision: 4bd25d0b81d1687d7f4be4c170e748277856f33c
URL: https://github.com/llvm/llvm-project/commit/4bd25d0b81d1687d7f4be4c170e748277856f33c
DIFF: https://github.com/llvm/llvm-project/commit/4bd25d0b81d1687d7f4be4c170e748277856f33c.diff
LOG: [mlir][spirv] Refresh base definitions to latest spec (v1.6)
This commit updates all SPIR-V enum definitions to match the latest
specification (v1.6 revision 2). Along the way, fixed some issues
in `gen_spirv_dialect.py` and added a new script for refreshing
all op definitions for such cases.
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D131293
Added:
mlir/utils/spirv/refresh_inst.sh
Modified:
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp
mlir/test/Dialect/SPIRV/IR/availability.mlir
mlir/utils/spirv/gen_spirv_dialect.py
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
index f8140fda5823c..7654c528b75de 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
@@ -304,7 +304,7 @@ def SPV_AtomicFAddEXTOp : SPV_Op<"AtomicFAddEXT", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_EXT_shader_atomic_float_add]>,
Capability<[SPV_C_AtomicFloat16AddEXT, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index 985498b42fce5..394ce1e917dff 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -130,9 +130,11 @@ def SPV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">;
def SPV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">;
def SPV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">;
def SPV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">;
+def SPV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">;
def SPV_VersionAttr : SPV_I32EnumAttr<"Version", "valid SPIR-V version", [
- SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5]>;
+ SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5,
+ SPV_V_1_6]>;
class MinVersion<I32EnumAttrCase min> : MinVersionBase<
"QueryMinVersionInterface", SPV_VersionAttr, min> {
@@ -336,77 +338,84 @@ def SPV_KHR_ray_query : I32EnumAttrCase<"SPV_KHR_ray_quer
def SPV_KHR_ray_tracing : I32EnumAttrCase<"SPV_KHR_ray_tracing", 22>;
def SPV_KHR_subgroup_uniform_control_flow : I32EnumAttrCase<"SPV_KHR_subgroup_uniform_control_flow", 23>;
def SPV_KHR_linkonce_odr : I32EnumAttrCase<"SPV_KHR_linkonce_odr", 24>;
-
-def SPV_EXT_demote_to_helper_invocation : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 25>;
-def SPV_EXT_descriptor_indexing : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 26>;
-def SPV_EXT_fragment_fully_covered : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 27>;
-def SPV_EXT_fragment_invocation_density : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 28>;
-def SPV_EXT_fragment_shader_interlock : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 29>;
-def SPV_EXT_physical_storage_buffer : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 30>;
-def SPV_EXT_shader_stencil_export : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 31>;
-def SPV_EXT_shader_viewport_index_layer : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 32>;
-def SPV_EXT_shader_atomic_float_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 33>;
-def SPV_EXT_shader_atomic_float_min_max : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 34>;
-def SPV_EXT_shader_image_int64 : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 35>;
-def SPV_EXT_shader_atomic_float16_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 36>;
-
-def SPV_AMD_gpu_shader_half_float_fetch : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 37>;
-def SPV_AMD_shader_ballot : I32EnumAttrCase<"SPV_AMD_shader_ballot", 38>;
-def SPV_AMD_shader_explicit_vertex_parameter : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 39>;
-def SPV_AMD_shader_fragment_mask : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 40>;
-def SPV_AMD_shader_image_load_store_lod : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 41>;
-def SPV_AMD_texture_gather_bias_lod : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 42>;
-
-def SPV_GOOGLE_decorate_string : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 43>;
-def SPV_GOOGLE_hlsl_functionality1 : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 44>;
-def SPV_GOOGLE_user_type : I32EnumAttrCase<"SPV_GOOGLE_user_type", 45>;
-
-def SPV_INTEL_device_side_avc_motion_estimation : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 46>;
-def SPV_INTEL_media_block_io : I32EnumAttrCase<"SPV_INTEL_media_block_io", 47>;
-def SPV_INTEL_shader_integer_functions2 : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 48>;
-def SPV_INTEL_subgroups : I32EnumAttrCase<"SPV_INTEL_subgroups", 49>;
-def SPV_INTEL_float_controls2 : I32EnumAttrCase<"SPV_INTEL_float_controls2", 50>;
-def SPV_INTEL_function_pointers : I32EnumAttrCase<"SPV_INTEL_function_pointers", 51>;
-def SPV_INTEL_inline_assembly : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 52>;
-def SPV_INTEL_vector_compute : I32EnumAttrCase<"SPV_INTEL_vector_compute", 53>;
-def SPV_INTEL_variable_length_array : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 54>;
-def SPV_INTEL_fpga_memory_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 55>;
-def SPV_INTEL_arbitrary_precision_integers : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 56>;
-def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 57>;
-def SPV_INTEL_unstructured_loop_controls : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 58>;
-def SPV_INTEL_fpga_loop_controls : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 59>;
-def SPV_INTEL_kernel_attributes : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 60>;
-def SPV_INTEL_fpga_memory_accesses : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 61>;
-def SPV_INTEL_fpga_cluster_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 62>;
-def SPV_INTEL_loop_fuse : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 63>;
-def SPV_INTEL_fpga_buffer_location : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 64>;
-def SPV_INTEL_arbitrary_precision_fixed_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 65>;
-def SPV_INTEL_usm_storage_classes : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 66>;
-def SPV_INTEL_io_pipes : I32EnumAttrCase<"SPV_INTEL_io_pipes", 67>;
-def SPV_INTEL_blocking_pipes : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 68>;
-def SPV_INTEL_fpga_reg : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 69>;
-def SPV_INTEL_long_constant_composite : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 70>;
-def SPV_INTEL_optnone : I32EnumAttrCase<"SPV_INTEL_optnone", 71>;
-def SPV_INTEL_debug_module : I32EnumAttrCase<"SPV_INTEL_debug_module", 72>;
-def SPV_INTEL_fp_fast_math_mode : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 73>;
-
-def SPV_NV_compute_shader_derivatives : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 74>;
-def SPV_NV_cooperative_matrix : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 75>;
-def SPV_NV_fragment_shader_barycentric : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 76>;
-def SPV_NV_geometry_shader_passthrough : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 77>;
-def SPV_NV_mesh_shader : I32EnumAttrCase<"SPV_NV_mesh_shader", 78>;
-def SPV_NV_ray_tracing : I32EnumAttrCase<"SPV_NV_ray_tracing", 79>;
-def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 80>;
-def SPV_NV_shader_image_footprint : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 81>;
-def SPV_NV_shader_sm_builtins : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 82>;
-def SPV_NV_shader_subgroup_partitioned : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 83>;
-def SPV_NV_shading_rate : I32EnumAttrCase<"SPV_NV_shading_rate", 84>;
-def SPV_NV_stereo_view_rendering : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 85>;
-def SPV_NV_viewport_array2 : I32EnumAttrCase<"SPV_NV_viewport_array2", 86>;
-def SPV_NV_bindless_texture : I32EnumAttrCase<"SPV_NV_bindless_texture", 87>;
-def SPV_NV_ray_tracing_motion_blur : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 88>;
-
-def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 89>;
+def SPV_KHR_fragment_shader_barycentric : I32EnumAttrCase<"SPV_KHR_fragment_shader_barycentric", 25>;
+def SPV_KHR_ray_cull_mask : I32EnumAttrCase<"SPV_KHR_ray_cull_mask", 26>;
+def SPV_KHR_uniform_group_instructions : I32EnumAttrCase<"SPV_KHR_uniform_group_instructions", 27>;
+def SPV_KHR_subgroup_rotate : I32EnumAttrCase<"SPV_KHR_subgroup_rotate", 28>;
+
+def SPV_EXT_demote_to_helper_invocation : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 1000>;
+def SPV_EXT_descriptor_indexing : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 1001>;
+def SPV_EXT_fragment_fully_covered : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 1002>;
+def SPV_EXT_fragment_invocation_density : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 1003>;
+def SPV_EXT_fragment_shader_interlock : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 1004>;
+def SPV_EXT_physical_storage_buffer : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 1005>;
+def SPV_EXT_shader_stencil_export : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 1006>;
+def SPV_EXT_shader_viewport_index_layer : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 1007>;
+def SPV_EXT_shader_atomic_float_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 1008>;
+def SPV_EXT_shader_atomic_float_min_max : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 1009>;
+def SPV_EXT_shader_image_int64 : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 1010>;
+def SPV_EXT_shader_atomic_float16_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 1011>;
+
+def SPV_AMD_gpu_shader_half_float_fetch : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 2000>;
+def SPV_AMD_shader_ballot : I32EnumAttrCase<"SPV_AMD_shader_ballot", 2001>;
+def SPV_AMD_shader_explicit_vertex_parameter : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 2002>;
+def SPV_AMD_shader_fragment_mask : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 2003>;
+def SPV_AMD_shader_image_load_store_lod : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 2004>;
+def SPV_AMD_texture_gather_bias_lod : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 2005>;
+def SPV_AMD_shader_early_and_late_fragment_tests : I32EnumAttrCase<"SPV_AMD_shader_early_and_late_fragment_tests", 2006>;
+
+def SPV_GOOGLE_decorate_string : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 3000>;
+def SPV_GOOGLE_hlsl_functionality1 : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 3001>;
+def SPV_GOOGLE_user_type : I32EnumAttrCase<"SPV_GOOGLE_user_type", 3002>;
+
+def SPV_INTEL_device_side_avc_motion_estimation : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 4000>;
+def SPV_INTEL_media_block_io : I32EnumAttrCase<"SPV_INTEL_media_block_io", 4001>;
+def SPV_INTEL_shader_integer_functions2 : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 4002>;
+def SPV_INTEL_subgroups : I32EnumAttrCase<"SPV_INTEL_subgroups", 4003>;
+def SPV_INTEL_float_controls2 : I32EnumAttrCase<"SPV_INTEL_float_controls2", 4004>;
+def SPV_INTEL_function_pointers : I32EnumAttrCase<"SPV_INTEL_function_pointers", 4005>;
+def SPV_INTEL_inline_assembly : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 4006>;
+def SPV_INTEL_vector_compute : I32EnumAttrCase<"SPV_INTEL_vector_compute", 4007>;
+def SPV_INTEL_variable_length_array : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 4008>;
+def SPV_INTEL_fpga_memory_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 4009>;
+def SPV_INTEL_arbitrary_precision_integers : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 4010>;
+def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 4011>;
+def SPV_INTEL_unstructured_loop_controls : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 4012>;
+def SPV_INTEL_fpga_loop_controls : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 4013>;
+def SPV_INTEL_kernel_attributes : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 4014>;
+def SPV_INTEL_fpga_memory_accesses : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 4015>;
+def SPV_INTEL_fpga_cluster_attributes : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 4016>;
+def SPV_INTEL_loop_fuse : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 4017>;
+def SPV_INTEL_fpga_buffer_location : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 4018>;
+def SPV_INTEL_arbitrary_precision_fixed_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 4019>;
+def SPV_INTEL_usm_storage_classes : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 4020>;
+def SPV_INTEL_io_pipes : I32EnumAttrCase<"SPV_INTEL_io_pipes", 4021>;
+def SPV_INTEL_blocking_pipes : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 4022>;
+def SPV_INTEL_fpga_reg : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>;
+def SPV_INTEL_long_constant_composite : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>;
+def SPV_INTEL_optnone : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>;
+def SPV_INTEL_debug_module : I32EnumAttrCase<"SPV_INTEL_debug_module", 4026>;
+def SPV_INTEL_fp_fast_math_mode : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 4027>;
+def SPV_INTEL_memory_access_aliasing : I32EnumAttrCase<"SPV_INTEL_memory_access_aliasing", 4028>;
+def SPV_INTEL_split_barrier : I32EnumAttrCase<"SPV_INTEL_split_barrier", 4029>;
+
+def SPV_NV_compute_shader_derivatives : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 5000>;
+def SPV_NV_cooperative_matrix : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 5001>;
+def SPV_NV_fragment_shader_barycentric : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 5002>;
+def SPV_NV_geometry_shader_passthrough : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 5003>;
+def SPV_NV_mesh_shader : I32EnumAttrCase<"SPV_NV_mesh_shader", 5004>;
+def SPV_NV_ray_tracing : I32EnumAttrCase<"SPV_NV_ray_tracing", 5005>;
+def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 5006>;
+def SPV_NV_shader_image_footprint : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 5007>;
+def SPV_NV_shader_sm_builtins : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 5008>;
+def SPV_NV_shader_subgroup_partitioned : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 5009>;
+def SPV_NV_shading_rate : I32EnumAttrCase<"SPV_NV_shading_rate", 5010>;
+def SPV_NV_stereo_view_rendering : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 5011>;
+def SPV_NV_viewport_array2 : I32EnumAttrCase<"SPV_NV_viewport_array2", 5012>;
+def SPV_NV_bindless_texture : I32EnumAttrCase<"SPV_NV_bindless_texture", 5013>;
+def SPV_NV_ray_tracing_motion_blur : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 5014>;
+
+def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 5015>;
def SPV_ExtensionAttr :
SPV_EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
@@ -420,6 +429,8 @@ def SPV_ExtensionAttr :
SPV_KHR_integer_dot_product, SPV_KHR_bit_instructions, SPV_KHR_fragment_shading_rate,
SPV_KHR_workgroup_memory_explicit_layout, SPV_KHR_ray_query,
SPV_KHR_ray_tracing, SPV_KHR_subgroup_uniform_control_flow, SPV_KHR_linkonce_odr,
+ SPV_KHR_fragment_shader_barycentric, SPV_KHR_ray_cull_mask,
+ SPV_KHR_uniform_group_instructions, SPV_KHR_subgroup_rotate,
SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_indexing,
SPV_EXT_fragment_fully_covered, SPV_EXT_fragment_invocation_density,
SPV_EXT_fragment_shader_interlock, SPV_EXT_physical_storage_buffer,
@@ -429,6 +440,7 @@ def SPV_ExtensionAttr :
SPV_AMD_gpu_shader_half_float_fetch, SPV_AMD_shader_ballot,
SPV_AMD_shader_explicit_vertex_parameter, SPV_AMD_shader_fragment_mask,
SPV_AMD_shader_image_load_store_lod, SPV_AMD_texture_gather_bias_lod,
+ SPV_AMD_shader_early_and_late_fragment_tests,
SPV_GOOGLE_decorate_string, SPV_GOOGLE_hlsl_functionality1, SPV_GOOGLE_user_type,
SPV_INTEL_device_side_avc_motion_estimation, SPV_INTEL_media_block_io,
SPV_INTEL_shader_integer_functions2, SPV_INTEL_subgroups, SPV_INTEL_vector_compute,
@@ -442,6 +454,7 @@ def SPV_ExtensionAttr :
SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes,
SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone,
SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode,
+ SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier,
SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix,
SPV_NV_fragment_shader_barycentric, SPV_NV_geometry_shader_passthrough,
SPV_NV_mesh_shader, SPV_NV_ray_tracing, SPV_NV_sample_mask_override_coverage,
@@ -488,6 +501,11 @@ def SPV_C_ShaderViewportIndex : I32EnumAttrCase<"ShaderV
MinVersion<SPV_V_1_5>
];
}
+def SPV_C_UniformDecoration : I32EnumAttrCase<"UniformDecoration", 71> {
+ list<Availability> availability = [
+ MinVersion<SPV_V_1_6>
+ ];
+}
def SPV_C_SubgroupBallotKHR : I32EnumAttrCase<"SubgroupBallotKHR", 4423> {
list<Availability> availability = [
Extension<[SPV_KHR_shader_ballot]>
@@ -568,9 +586,9 @@ def SPV_C_ImageFootprintNV : I32EnumAttrCase<"ImageFo
Extension<[SPV_NV_shader_image_footprint]>
];
}
-def SPV_C_FragmentBarycentricNV : I32EnumAttrCase<"FragmentBarycentricNV", 5284> {
+def SPV_C_FragmentBarycentricKHR : I32EnumAttrCase<"FragmentBarycentricKHR", 5284> {
list<Availability> availability = [
- Extension<[SPV_NV_fragment_shader_barycentric]>
+ Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>
];
}
def SPV_C_ComputeDerivativeGroupQuadsNV : I32EnumAttrCase<"ComputeDerivativeGroupQuadsNV", 5288> {
@@ -748,6 +766,11 @@ def SPV_C_LoopFuseINTEL : I32EnumAttrCase<"LoopFus
Extension<[SPV_INTEL_loop_fuse]>
];
}
+def SPV_C_MemoryAccessAliasingINTEL : I32EnumAttrCase<"MemoryAccessAliasingINTEL", 5910> {
+ list<Availability> availability = [
+ Extension<[SPV_INTEL_memory_access_aliasing]>
+ ];
+}
def SPV_C_FPGABufferLocationINTEL : I32EnumAttrCase<"FPGABufferLocationINTEL", 5920> {
list<Availability> availability = [
Extension<[SPV_INTEL_fpga_buffer_location]>
@@ -778,19 +801,24 @@ def SPV_C_FPGARegINTEL : I32EnumAttrCase<"FPGAReg
Extension<[SPV_INTEL_fpga_reg]>
];
}
-def SPV_C_DotProductInputAllKHR : I32EnumAttrCase<"DotProductInputAllKHR", 6016> {
+def SPV_C_DotProductInputAll : I32EnumAttrCase<"DotProductInputAll", 6016> {
list<Availability> availability = [
- Extension<[SPV_KHR_integer_dot_product]>
+ MinVersion<SPV_V_1_6>
];
}
-def SPV_C_DotProductInput4x8BitPackedKHR : I32EnumAttrCase<"DotProductInput4x8BitPackedKHR", 6018> {
+def SPV_C_DotProductInput4x8BitPacked : I32EnumAttrCase<"DotProductInput4x8BitPacked", 6018> {
list<Availability> availability = [
- Extension<[SPV_KHR_integer_dot_product]>
+ MinVersion<SPV_V_1_6>
];
}
-def SPV_C_DotProductKHR : I32EnumAttrCase<"DotProductKHR", 6019> {
+def SPV_C_DotProduct : I32EnumAttrCase<"DotProduct", 6019> {
list<Availability> availability = [
- Extension<[SPV_KHR_integer_dot_product]>
+ MinVersion<SPV_V_1_6>
+ ];
+}
+def SPV_C_RayCullMaskKHR : I32EnumAttrCase<"RayCullMaskKHR", 6020> {
+ list<Availability> availability = [
+ Extension<[SPV_KHR_ray_cull_mask]>
];
}
def SPV_C_BitInstructions : I32EnumAttrCase<"BitInstructions", 6025> {
@@ -798,6 +826,16 @@ def SPV_C_BitInstructions : I32EnumAttrCase<"BitInst
Extension<[SPV_KHR_bit_instructions]>
];
}
+def SPV_C_AtomicFloat32AddEXT : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
+ list<Availability> availability = [
+ Extension<[SPV_EXT_shader_atomic_float_add]>
+ ];
+}
+def SPV_C_AtomicFloat64AddEXT : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
+ list<Availability> availability = [
+ Extension<[SPV_EXT_shader_atomic_float_add]>
+ ];
+}
def SPV_C_LongConstantCompositeINTEL : I32EnumAttrCase<"LongConstantCompositeINTEL", 6089> {
list<Availability> availability = [
Extension<[SPV_INTEL_long_constant_composite]>
@@ -808,11 +846,26 @@ def SPV_C_OptNoneINTEL : I32EnumAttrCase<"OptNone
Extension<[SPV_INTEL_optnone]>
];
}
+def SPV_C_AtomicFloat16AddEXT : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
+ list<Availability> availability = [
+ Extension<[SPV_EXT_shader_atomic_float16_add]>
+ ];
+}
def SPV_C_DebugInfoModuleINTEL : I32EnumAttrCase<"DebugInfoModuleINTEL", 6114> {
list<Availability> availability = [
Extension<[SPV_INTEL_debug_module]>
];
}
+def SPV_C_SplitBarrierINTEL : I32EnumAttrCase<"SplitBarrierINTEL", 6141> {
+ list<Availability> availability = [
+ Extension<[SPV_INTEL_split_barrier]>
+ ];
+}
+def SPV_C_GroupUniformArithmeticKHR : I32EnumAttrCase<"GroupUniformArithmeticKHR", 6400> {
+ list<Availability> availability = [
+ Extension<[SPV_KHR_uniform_group_instructions]>
+ ];
+}
def SPV_C_Shader : I32EnumAttrCase<"Shader", 1> {
list<I32EnumAttrCase> implies = [SPV_C_Matrix];
}
@@ -924,10 +977,16 @@ def SPV_C_FPFastMathModeINTEL : I32EnumAttrCase<"FPFastM
Extension<[SPV_INTEL_fp_fast_math_mode]>
];
}
-def SPV_C_DotProductInput4x8BitKHR : I32EnumAttrCase<"DotProductInput4x8BitKHR", 6017> {
+def SPV_C_DotProductInput4x8Bit : I32EnumAttrCase<"DotProductInput4x8Bit", 6017> {
list<I32EnumAttrCase> implies = [SPV_C_Int8];
list<Availability> availability = [
- Extension<[SPV_KHR_integer_dot_product]>
+ MinVersion<SPV_V_1_6>
+ ];
+}
+def SPV_C_GroupNonUniformRotateKHR : I32EnumAttrCase<"GroupNonUniformRotateKHR", 6026> {
+ list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+ list<Availability> availability = [
+ Extension<[SPV_KHR_subgroup_rotate]>
];
}
def SPV_C_Geometry : I32EnumAttrCase<"Geometry", 2> {
@@ -1209,10 +1268,10 @@ def SPV_C_FragmentShaderPixelInterlockEXT : I32EnumAttrCase<"Fragmen
Extension<[SPV_EXT_fragment_shader_interlock]>
];
}
-def SPV_C_DemoteToHelperInvocationEXT : I32EnumAttrCase<"DemoteToHelperInvocationEXT", 5379> {
+def SPV_C_DemoteToHelperInvocation : I32EnumAttrCase<"DemoteToHelperInvocation", 5379> {
list<I32EnumAttrCase> implies = [SPV_C_Shader];
list<Availability> availability = [
- Extension<[SPV_EXT_demote_to_helper_invocation]>
+ MinVersion<SPV_V_1_6>
];
}
def SPV_C_IntegerFunctions2INTEL : I32EnumAttrCase<"IntegerFunctions2INTEL", 5584> {
@@ -1221,27 +1280,6 @@ def SPV_C_IntegerFunctions2INTEL : I32EnumAttrCase<"Integer
Extension<[SPV_INTEL_shader_integer_functions2]>
];
}
-def SPV_C_AtomicFloat32AddEXT : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
- // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
- // list<I32EnumAttrCase> implies = [SPV_C_Shader];
- list<Availability> availability = [
- Extension<[SPV_EXT_shader_atomic_float_add]>
- ];
-}
-def SPV_C_AtomicFloat64AddEXT : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
- // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
- // list<I32EnumAttrCase> implies = [SPV_C_Shader];
- list<Availability> availability = [
- Extension<[SPV_EXT_shader_atomic_float_add]>
- ];
-}
-def SPV_C_AtomicFloat16AddEXT : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
- // Float atomics also supported in kernels (https://github.com/KhronosGroup/SPIRV-Headers/pull/257).
- // list<I32EnumAttrCase> implies = [SPV_C_Shader];
- list<Availability> availability = [
- Extension<[SPV_EXT_shader_atomic_float16_add]>
- ];
-}
def SPV_C_TessellationPointSize : I32EnumAttrCase<"TessellationPointSize", 23> {
list<I32EnumAttrCase> implies = [SPV_C_Tessellation];
}
@@ -1368,22 +1406,23 @@ def SPV_CapabilityAttr :
SPV_C_Matrix, SPV_C_Addresses, SPV_C_Linkage, SPV_C_Kernel, SPV_C_Float16,
SPV_C_Float64, SPV_C_Int64, SPV_C_Groups, SPV_C_Int16, SPV_C_Int8,
SPV_C_Sampled1D, SPV_C_SampledBuffer, SPV_C_GroupNonUniform, SPV_C_ShaderLayer,
- SPV_C_ShaderViewportIndex, SPV_C_SubgroupBallotKHR, SPV_C_SubgroupVoteKHR,
- SPV_C_StorageBuffer16BitAccess, SPV_C_StoragePushConstant16,
- SPV_C_StorageInputOutput16, SPV_C_DeviceGroup, SPV_C_AtomicStorageOps,
- SPV_C_SampleMaskPostDepthCoverage, SPV_C_StorageBuffer8BitAccess,
- SPV_C_StoragePushConstant8, SPV_C_DenormPreserve, SPV_C_DenormFlushToZero,
- SPV_C_SignedZeroInfNanPreserve, SPV_C_RoundingModeRTE, SPV_C_RoundingModeRTZ,
- SPV_C_ImageFootprintNV, SPV_C_FragmentBarycentricNV,
- SPV_C_ComputeDerivativeGroupQuadsNV, SPV_C_GroupNonUniformPartitionedNV,
- SPV_C_VulkanMemoryModel, SPV_C_VulkanMemoryModelDeviceScope,
- SPV_C_ComputeDerivativeGroupLinearNV, SPV_C_BindlessTextureNV,
- SPV_C_SubgroupShuffleINTEL, SPV_C_SubgroupBufferBlockIOINTEL,
- SPV_C_SubgroupImageBlockIOINTEL, SPV_C_SubgroupImageMediaBlockIOINTEL,
- SPV_C_RoundToInfinityINTEL, SPV_C_FloatingPointModeINTEL,
- SPV_C_FunctionPointersINTEL, SPV_C_IndirectReferencesINTEL, SPV_C_AsmINTEL,
- SPV_C_AtomicFloat32MinMaxEXT, SPV_C_AtomicFloat64MinMaxEXT,
- SPV_C_AtomicFloat16MinMaxEXT, SPV_C_VectorAnyINTEL, SPV_C_ExpectAssumeKHR,
+ SPV_C_ShaderViewportIndex, SPV_C_UniformDecoration, SPV_C_SubgroupBallotKHR,
+ SPV_C_SubgroupVoteKHR, SPV_C_StorageBuffer16BitAccess,
+ SPV_C_StoragePushConstant16, SPV_C_StorageInputOutput16, SPV_C_DeviceGroup,
+ SPV_C_AtomicStorageOps, SPV_C_SampleMaskPostDepthCoverage,
+ SPV_C_StorageBuffer8BitAccess, SPV_C_StoragePushConstant8,
+ SPV_C_DenormPreserve, SPV_C_DenormFlushToZero, SPV_C_SignedZeroInfNanPreserve,
+ SPV_C_RoundingModeRTE, SPV_C_RoundingModeRTZ, SPV_C_ImageFootprintNV,
+ SPV_C_FragmentBarycentricKHR, SPV_C_ComputeDerivativeGroupQuadsNV,
+ SPV_C_GroupNonUniformPartitionedNV, SPV_C_VulkanMemoryModel,
+ SPV_C_VulkanMemoryModelDeviceScope, SPV_C_ComputeDerivativeGroupLinearNV,
+ SPV_C_BindlessTextureNV, SPV_C_SubgroupShuffleINTEL,
+ SPV_C_SubgroupBufferBlockIOINTEL, SPV_C_SubgroupImageBlockIOINTEL,
+ SPV_C_SubgroupImageMediaBlockIOINTEL, SPV_C_RoundToInfinityINTEL,
+ SPV_C_FloatingPointModeINTEL, SPV_C_FunctionPointersINTEL,
+ SPV_C_IndirectReferencesINTEL, SPV_C_AsmINTEL, SPV_C_AtomicFloat32MinMaxEXT,
+ SPV_C_AtomicFloat64MinMaxEXT, SPV_C_AtomicFloat16MinMaxEXT,
+ SPV_C_VectorAnyINTEL, SPV_C_ExpectAssumeKHR,
SPV_C_SubgroupAvcMotionEstimationINTEL,
SPV_C_SubgroupAvcMotionEstimationIntraINTEL,
SPV_C_SubgroupAvcMotionEstimationChromaINTEL, SPV_C_VariableLengthArrayINTEL,
@@ -1393,12 +1432,15 @@ def SPV_CapabilityAttr :
SPV_C_UnstructuredLoopControlsINTEL, SPV_C_FPGALoopControlsINTEL,
SPV_C_KernelAttributesINTEL, SPV_C_FPGAKernelAttributesINTEL,
SPV_C_FPGAMemoryAccessesINTEL, SPV_C_FPGAClusterAttributesINTEL,
- SPV_C_LoopFuseINTEL, SPV_C_FPGABufferLocationINTEL,
- SPV_C_ArbitraryPrecisionFixedPointINTEL, SPV_C_USMStorageClassesINTEL,
- SPV_C_IOPipesINTEL, SPV_C_BlockingPipesINTEL, SPV_C_FPGARegINTEL,
- SPV_C_DotProductInputAllKHR, SPV_C_DotProductInput4x8BitPackedKHR,
- SPV_C_DotProductKHR, SPV_C_BitInstructions, SPV_C_LongConstantCompositeINTEL,
- SPV_C_OptNoneINTEL, SPV_C_DebugInfoModuleINTEL, SPV_C_Shader, SPV_C_Vector16,
+ SPV_C_LoopFuseINTEL, SPV_C_MemoryAccessAliasingINTEL,
+ SPV_C_FPGABufferLocationINTEL, SPV_C_ArbitraryPrecisionFixedPointINTEL,
+ SPV_C_USMStorageClassesINTEL, SPV_C_IOPipesINTEL, SPV_C_BlockingPipesINTEL,
+ SPV_C_FPGARegINTEL, SPV_C_DotProductInputAll,
+ SPV_C_DotProductInput4x8BitPacked, SPV_C_DotProduct, SPV_C_RayCullMaskKHR,
+ SPV_C_BitInstructions, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT,
+ SPV_C_LongConstantCompositeINTEL, SPV_C_OptNoneINTEL,
+ SPV_C_AtomicFloat16AddEXT, SPV_C_DebugInfoModuleINTEL, SPV_C_SplitBarrierINTEL,
+ SPV_C_GroupUniformArithmeticKHR, SPV_C_Shader, SPV_C_Vector16,
SPV_C_Float16Buffer, SPV_C_Int64Atomics, SPV_C_ImageBasic, SPV_C_Pipes,
SPV_C_DeviceEnqueue, SPV_C_LiteralSampler, SPV_C_GenericPointer, SPV_C_Image1D,
SPV_C_ImageBuffer, SPV_C_NamedBarrier, SPV_C_GroupNonUniformVote,
@@ -1407,9 +1449,10 @@ def SPV_CapabilityAttr :
SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformQuad,
SPV_C_StorageUniform16, SPV_C_UniformAndStorageBuffer8BitAccess,
SPV_C_UniformTexelBufferArrayDynamicIndexing, SPV_C_VectorComputeINTEL,
- SPV_C_FPFastMathModeINTEL, SPV_C_DotProductInput4x8BitKHR, SPV_C_Geometry,
- SPV_C_Tessellation, SPV_C_ImageReadWrite, SPV_C_ImageMipmap,
- SPV_C_AtomicStorage, SPV_C_ImageGatherExtended, SPV_C_StorageImageMultisample,
+ SPV_C_FPFastMathModeINTEL, SPV_C_DotProductInput4x8Bit,
+ SPV_C_GroupNonUniformRotateKHR, SPV_C_Geometry, SPV_C_Tessellation,
+ SPV_C_ImageReadWrite, SPV_C_ImageMipmap, SPV_C_AtomicStorage,
+ SPV_C_ImageGatherExtended, SPV_C_StorageImageMultisample,
SPV_C_UniformBufferArrayDynamicIndexing,
SPV_C_SampledImageArrayDynamicIndexing,
SPV_C_StorageBufferArrayDynamicIndexing,
@@ -1433,11 +1476,10 @@ def SPV_CapabilityAttr :
SPV_C_RayTracingProvisionalKHR, SPV_C_CooperativeMatrixNV,
SPV_C_FragmentShaderSampleInterlockEXT,
SPV_C_FragmentShaderShadingRateInterlockEXT, SPV_C_ShaderSMBuiltinsNV,
- SPV_C_FragmentShaderPixelInterlockEXT, SPV_C_DemoteToHelperInvocationEXT,
- SPV_C_IntegerFunctions2INTEL, SPV_C_AtomicFloat32AddEXT,
- SPV_C_AtomicFloat64AddEXT, SPV_C_AtomicFloat16AddEXT,
- SPV_C_TessellationPointSize, SPV_C_GeometryPointSize, SPV_C_ImageCubeArray,
- SPV_C_ImageRect, SPV_C_GeometryStreams, SPV_C_MultiViewport,
+ SPV_C_FragmentShaderPixelInterlockEXT, SPV_C_DemoteToHelperInvocation,
+ SPV_C_IntegerFunctions2INTEL, SPV_C_TessellationPointSize,
+ SPV_C_GeometryPointSize, SPV_C_ImageCubeArray, SPV_C_ImageRect,
+ SPV_C_GeometryStreams, SPV_C_MultiViewport,
SPV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR, SPV_C_VariablePointers,
SPV_C_RayTraversalPrimitiveCullingKHR, SPV_C_SampleMaskOverrideCoverageNV,
SPV_C_GeometryShaderPassthroughNV, SPV_C_PerViewAttributesNV,
@@ -1855,16 +1897,16 @@ def SPV_BI_MeshViewIndicesNV : I32EnumAttrCase<"MeshViewIndicesNV", 52
Capability<[SPV_C_MeshShadingNV]>
];
}
-def SPV_BI_BaryCoordNV : I32EnumAttrCase<"BaryCoordNV", 5286> {
+def SPV_BI_BaryCoordKHR : I32EnumAttrCase<"BaryCoordKHR", 5286> {
list<Availability> availability = [
- Extension<[SPV_NV_fragment_shader_barycentric]>,
- Capability<[SPV_C_FragmentBarycentricNV]>
+ Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+ Capability<[SPV_C_FragmentBarycentricKHR]>
];
}
-def SPV_BI_BaryCoordNoPerspNV : I32EnumAttrCase<"BaryCoordNoPerspNV", 5287> {
+def SPV_BI_BaryCoordNoPerspKHR : I32EnumAttrCase<"BaryCoordNoPerspKHR", 5287> {
list<Availability> availability = [
- Extension<[SPV_NV_fragment_shader_barycentric]>,
- Capability<[SPV_C_FragmentBarycentricNV]>
+ Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+ Capability<[SPV_C_FragmentBarycentricKHR]>
];
}
def SPV_BI_FragSizeEXT : I32EnumAttrCase<"FragSizeEXT", 5292> {
@@ -1999,6 +2041,12 @@ def SPV_BI_SMIDNV : I32EnumAttrCase<"SMIDNV", 5377> {
Capability<[SPV_C_ShaderSMBuiltinsNV]>
];
}
+def SPV_BI_CullMaskKHR : I32EnumAttrCase<"CullMaskKHR", 6021> {
+ list<Availability> availability = [
+ Extension<[SPV_KHR_ray_cull_mask]>,
+ Capability<[SPV_C_RayCullMaskKHR]>
+ ];
+}
def SPV_BuiltInAttr :
SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", [
@@ -2028,7 +2076,7 @@ def SPV_BuiltInAttr :
SPV_BI_TaskCountNV, SPV_BI_PrimitiveCountNV, SPV_BI_PrimitiveIndicesNV,
SPV_BI_ClipDistancePerViewNV, SPV_BI_CullDistancePerViewNV,
SPV_BI_LayerPerViewNV, SPV_BI_MeshViewCountNV, SPV_BI_MeshViewIndicesNV,
- SPV_BI_BaryCoordNV, SPV_BI_BaryCoordNoPerspNV, SPV_BI_FragSizeEXT,
+ SPV_BI_BaryCoordKHR, SPV_BI_BaryCoordNoPerspKHR, SPV_BI_FragSizeEXT,
SPV_BI_FragInvocationCountEXT, SPV_BI_LaunchIdKHR, SPV_BI_LaunchSizeKHR,
SPV_BI_WorldRayOriginKHR, SPV_BI_WorldRayDirectionKHR,
SPV_BI_ObjectRayOriginKHR, SPV_BI_ObjectRayDirectionKHR, SPV_BI_RayTminKHR,
@@ -2036,7 +2084,7 @@ def SPV_BuiltInAttr :
SPV_BI_WorldToObjectKHR, SPV_BI_HitTNV, SPV_BI_HitKindKHR,
SPV_BI_CurrentRayTimeNV, SPV_BI_IncomingRayFlagsKHR,
SPV_BI_RayGeometryIndexKHR, SPV_BI_WarpsPerSMNV, SPV_BI_SMCountNV,
- SPV_BI_WarpIDNV, SPV_BI_SMIDNV
+ SPV_BI_WarpIDNV, SPV_BI_SMIDNV, SPV_BI_CullMaskKHR
]>;
def SPV_D_RelaxedPrecision : I32EnumAttrCase<"RelaxedPrecision", 0> {
@@ -2080,12 +2128,12 @@ def SPV_D_MatrixStride : I32EnumAttrCase<"MatrixStride", 7
Capability<[SPV_C_Matrix]>
];
}
-def SPV_D_GLShared : I32EnumAttrCase<"GLShared", 8> {
+def SPV_D_GLSLShared : I32EnumAttrCase<"GLSLShared", 8> {
list<Availability> availability = [
Capability<[SPV_C_Shader]>
];
}
-def SPV_D_GLPacked : I32EnumAttrCase<"GLPacked", 9> {
+def SPV_D_GLSLPacked : I32EnumAttrCase<"GLSLPacked", 9> {
list<Availability> availability = [
Capability<[SPV_C_Shader]>
];
@@ -2139,13 +2187,13 @@ def SPV_D_NonWritable : I32EnumAttrCase<"NonWritable", 24
def SPV_D_NonReadable : I32EnumAttrCase<"NonReadable", 25>;
def SPV_D_Uniform : I32EnumAttrCase<"Uniform", 26> {
list<Availability> availability = [
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
];
}
def SPV_D_UniformId : I32EnumAttrCase<"UniformId", 27> {
list<Availability> availability = [
MinVersion<SPV_V_1_4>,
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
];
}
def SPV_D_SaturatedConversion : I32EnumAttrCase<"SaturatedConversion", 28> {
@@ -2303,10 +2351,10 @@ def SPV_D_PerTaskNV : I32EnumAttrCase<"PerTaskNV", 5273
Capability<[SPV_C_MeshShadingNV]>
];
}
-def SPV_D_PerVertexNV : I32EnumAttrCase<"PerVertexNV", 5285> {
+def SPV_D_PerVertexKHR : I32EnumAttrCase<"PerVertexKHR", 5285> {
list<Availability> availability = [
- Extension<[SPV_NV_fragment_shader_barycentric]>,
- Capability<[SPV_C_FragmentBarycentricNV]>
+ Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
+ Capability<[SPV_C_FragmentBarycentricKHR]>
];
}
def SPV_D_NonUniform : I32EnumAttrCase<"NonUniform", 5300> {
@@ -2520,6 +2568,16 @@ def SPV_D_FuseLoopsInFunctionINTEL : I32EnumAttrCase<"FuseLoopsInFunct
Capability<[SPV_C_LoopFuseINTEL]>
];
}
+def SPV_D_AliasScopeINTEL : I32EnumAttrCase<"AliasScopeINTEL", 5914> {
+ list<Availability> availability = [
+ Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+ ];
+}
+def SPV_D_NoAliasINTEL : I32EnumAttrCase<"NoAliasINTEL", 5915> {
+ list<Availability> availability = [
+ Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+ ];
+}
def SPV_D_BufferLocationINTEL : I32EnumAttrCase<"BufferLocationINTEL", 5921> {
list<Availability> availability = [
Capability<[SPV_C_FPGABufferLocationINTEL]>
@@ -2545,12 +2603,17 @@ def SPV_D_VectorComputeCallableFunctionINTEL : I32EnumAttrCase<"VectorComputeCal
Capability<[SPV_C_VectorComputeINTEL]>
];
}
+def SPV_D_MediaBlockIOINTEL : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> {
+ list<Availability> availability = [
+ Capability<[SPV_C_VectorComputeINTEL]>
+ ];
+}
def SPV_DecorationAttr :
SPV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", [
SPV_D_RelaxedPrecision, SPV_D_SpecId, SPV_D_Block, SPV_D_BufferBlock,
SPV_D_RowMajor, SPV_D_ColMajor, SPV_D_ArrayStride, SPV_D_MatrixStride,
- SPV_D_GLShared, SPV_D_GLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
+ SPV_D_GLSLShared, SPV_D_GLSLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
SPV_D_NoPerspective, SPV_D_Flat, SPV_D_Patch, SPV_D_Centroid, SPV_D_Sample,
SPV_D_Invariant, SPV_D_Restrict, SPV_D_Aliased, SPV_D_Volatile, SPV_D_Constant,
SPV_D_Coherent, SPV_D_NonWritable, SPV_D_NonReadable, SPV_D_Uniform,
@@ -2563,7 +2626,7 @@ def SPV_DecorationAttr :
SPV_D_NoUnsignedWrap, SPV_D_ExplicitInterpAMD, SPV_D_OverrideCoverageNV,
SPV_D_PassthroughNV, SPV_D_ViewportRelativeNV,
SPV_D_SecondaryViewportRelativeNV, SPV_D_PerPrimitiveNV, SPV_D_PerViewNV,
- SPV_D_PerTaskNV, SPV_D_PerVertexNV, SPV_D_NonUniform, SPV_D_RestrictPointer,
+ SPV_D_PerTaskNV, SPV_D_PerVertexKHR, SPV_D_NonUniform, SPV_D_RestrictPointer,
SPV_D_AliasedPointer, SPV_D_BindlessSamplerNV, SPV_D_BindlessImageNV,
SPV_D_BoundSamplerNV, SPV_D_BoundImageNV, SPV_D_SIMTCallINTEL,
SPV_D_ReferencedIndirectlyINTEL, SPV_D_ClobberINTEL, SPV_D_SideEffectsINTEL,
@@ -2577,9 +2640,10 @@ def SPV_DecorationAttr :
SPV_D_SimpleDualPortINTEL, SPV_D_MergeINTEL, SPV_D_BankBitsINTEL,
SPV_D_ForcePow2DepthINTEL, SPV_D_BurstCoalesceINTEL, SPV_D_CacheSizeINTEL,
SPV_D_DontStaticallyCoalesceINTEL, SPV_D_PrefetchINTEL, SPV_D_StallEnableINTEL,
- SPV_D_FuseLoopsInFunctionINTEL, SPV_D_BufferLocationINTEL,
- SPV_D_IOPipeStorageINTEL, SPV_D_FunctionFloatingPointModeINTEL,
- SPV_D_SingleElementVectorINTEL, SPV_D_VectorComputeCallableFunctionINTEL
+ SPV_D_FuseLoopsInFunctionINTEL, SPV_D_AliasScopeINTEL, SPV_D_NoAliasINTEL,
+ SPV_D_BufferLocationINTEL, SPV_D_IOPipeStorageINTEL,
+ SPV_D_FunctionFloatingPointModeINTEL, SPV_D_SingleElementVectorINTEL,
+ SPV_D_VectorComputeCallableFunctionINTEL, SPV_D_MediaBlockIOINTEL
]>;
def SPV_D_1D : I32EnumAttrCase<"Dim1D", 0> {
@@ -2854,12 +2918,54 @@ def SPV_EM_RoundingModeRTZ : I32EnumAttrCase<"RoundingModeRTZ",
Capability<[SPV_C_RoundingModeRTZ]>
];
}
+def SPV_EM_EarlyAndLateFragmentTestsAMD : I32EnumAttrCase<"EarlyAndLateFragmentTestsAMD", 5017> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests]>,
+ Capability<[SPV_C_Shader]>
+ ];
+}
def SPV_EM_StencilRefReplacingEXT : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> {
list<Availability> availability = [
Extension<[SPV_EXT_shader_stencil_export]>,
Capability<[SPV_C_StencilExportEXT]>
];
}
+def SPV_EM_StencilRefUnchangedFrontAMD : I32EnumAttrCase<"StencilRefUnchangedFrontAMD", 5079> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
+def SPV_EM_StencilRefGreaterFrontAMD : I32EnumAttrCase<"StencilRefGreaterFrontAMD", 5080> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
+def SPV_EM_StencilRefLessFrontAMD : I32EnumAttrCase<"StencilRefLessFrontAMD", 5081> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
+def SPV_EM_StencilRefUnchangedBackAMD : I32EnumAttrCase<"StencilRefUnchangedBackAMD", 5082> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
+def SPV_EM_StencilRefGreaterBackAMD : I32EnumAttrCase<"StencilRefGreaterBackAMD", 5083> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
+def SPV_EM_StencilRefLessBackAMD : I32EnumAttrCase<"StencilRefLessBackAMD", 5084> {
+ list<Availability> availability = [
+ Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
+ Capability<[SPV_C_StencilExportEXT]>
+ ];
+}
def SPV_EM_OutputLinesNV : I32EnumAttrCase<"OutputLinesNV", 5269> {
list<Availability> availability = [
Extension<[SPV_NV_mesh_shader]>,
@@ -2980,6 +3086,11 @@ def SPV_EM_SchedulerTargetFmaxMhzINTEL : I32EnumAttrCase<"SchedulerTargetFm
Capability<[SPV_C_FPGAKernelAttributesINTEL]>
];
}
+def SPV_EM_NamedBarrierCountINTEL : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
+ list<Availability> availability = [
+ Capability<[SPV_C_VectorComputeINTEL]>
+ ];
+}
def SPV_ExecutionModeAttr :
SPV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", [
@@ -2998,17 +3109,21 @@ def SPV_ExecutionModeAttr :
SPV_EM_SubgroupUniformControlFlowKHR, SPV_EM_PostDepthCoverage,
SPV_EM_DenormPreserve, SPV_EM_DenormFlushToZero,
SPV_EM_SignedZeroInfNanPreserve, SPV_EM_RoundingModeRTE,
- SPV_EM_RoundingModeRTZ, SPV_EM_StencilRefReplacingEXT, SPV_EM_OutputLinesNV,
- SPV_EM_OutputPrimitivesNV, SPV_EM_DerivativeGroupQuadsNV,
- SPV_EM_DerivativeGroupLinearNV, SPV_EM_OutputTrianglesNV,
- SPV_EM_PixelInterlockOrderedEXT, SPV_EM_PixelInterlockUnorderedEXT,
- SPV_EM_SampleInterlockOrderedEXT, SPV_EM_SampleInterlockUnorderedEXT,
- SPV_EM_ShadingRateInterlockOrderedEXT, SPV_EM_ShadingRateInterlockUnorderedEXT,
- SPV_EM_SharedLocalMemorySizeINTEL, SPV_EM_RoundingModeRTPINTEL,
- SPV_EM_RoundingModeRTNINTEL, SPV_EM_FloatingPointModeALTINTEL,
- SPV_EM_FloatingPointModeIEEEINTEL, SPV_EM_MaxWorkgroupSizeINTEL,
- SPV_EM_MaxWorkDimINTEL, SPV_EM_NoGlobalOffsetINTEL,
- SPV_EM_NumSIMDWorkitemsINTEL, SPV_EM_SchedulerTargetFmaxMhzINTEL
+ SPV_EM_RoundingModeRTZ, SPV_EM_EarlyAndLateFragmentTestsAMD,
+ SPV_EM_StencilRefReplacingEXT, SPV_EM_StencilRefUnchangedFrontAMD,
+ SPV_EM_StencilRefGreaterFrontAMD, SPV_EM_StencilRefLessFrontAMD,
+ SPV_EM_StencilRefUnchangedBackAMD, SPV_EM_StencilRefGreaterBackAMD,
+ SPV_EM_StencilRefLessBackAMD, SPV_EM_OutputLinesNV, SPV_EM_OutputPrimitivesNV,
+ SPV_EM_DerivativeGroupQuadsNV, SPV_EM_DerivativeGroupLinearNV,
+ SPV_EM_OutputTrianglesNV, SPV_EM_PixelInterlockOrderedEXT,
+ SPV_EM_PixelInterlockUnorderedEXT, SPV_EM_SampleInterlockOrderedEXT,
+ SPV_EM_SampleInterlockUnorderedEXT, SPV_EM_ShadingRateInterlockOrderedEXT,
+ SPV_EM_ShadingRateInterlockUnorderedEXT, SPV_EM_SharedLocalMemorySizeINTEL,
+ SPV_EM_RoundingModeRTPINTEL, SPV_EM_RoundingModeRTNINTEL,
+ SPV_EM_FloatingPointModeALTINTEL, SPV_EM_FloatingPointModeIEEEINTEL,
+ SPV_EM_MaxWorkgroupSizeINTEL, SPV_EM_MaxWorkDimINTEL,
+ SPV_EM_NoGlobalOffsetINTEL, SPV_EM_NumSIMDWorkitemsINTEL,
+ SPV_EM_SchedulerTargetFmaxMhzINTEL, SPV_EM_NamedBarrierCountINTEL
]>;
def SPV_EM_Vertex : I32EnumAttrCase<"Vertex", 0> {
@@ -3439,13 +3554,19 @@ def SPV_IO_ZeroExtend : I32BitEnumAttrCaseBit<"ZeroExtend", 13> {
MinVersion<SPV_V_1_4>
];
}
+def SPV_IO_Nontemporal : I32BitEnumAttrCaseBit<"Nontemporal", 14> {
+ list<Availability> availability = [
+ MinVersion<SPV_V_1_6>
+ ];
+}
def SPV_ImageOperandsAttr :
SPV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", [
SPV_IO_None, SPV_IO_Bias, SPV_IO_Lod, SPV_IO_Grad, SPV_IO_ConstOffset,
SPV_IO_Offset, SPV_IO_ConstOffsets, SPV_IO_Sample, SPV_IO_MinLod,
SPV_IO_MakeTexelAvailable, SPV_IO_MakeTexelVisible, SPV_IO_NonPrivateTexel,
- SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend
+ SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend,
+ SPV_IO_Nontemporal
]>;
def SPV_LT_Export : I32EnumAttrCase<"Export", 0> {
@@ -3590,12 +3711,24 @@ def SPV_MA_NonPrivatePointer : I32BitEnumAttrCaseBit<"NonPrivatePointer", 5>
Capability<[SPV_C_VulkanMemoryModel]>
];
}
+def SPV_MA_AliasScopeINTELMask : I32BitEnumAttrCaseBit<"AliasScopeINTELMask", 16> {
+ list<Availability> availability = [
+ Extension<[SPV_INTEL_memory_access_aliasing]>,
+ Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+ ];
+}
+def SPV_MA_NoAliasINTELMask : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> {
+ list<Availability> availability = [
+ Extension<[SPV_INTEL_memory_access_aliasing]>,
+ Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+ ];
+}
def SPV_MemoryAccessAttr :
SPV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", [
SPV_MA_None, SPV_MA_Volatile, SPV_MA_Aligned, SPV_MA_Nontemporal,
SPV_MA_MakePointerAvailable, SPV_MA_MakePointerVisible,
- SPV_MA_NonPrivatePointer
+ SPV_MA_NonPrivatePointer, SPV_MA_AliasScopeINTELMask, SPV_MA_NoAliasINTELMask
]>;
def SPV_MM_Simple : I32EnumAttrCase<"Simple", 0> {
@@ -4279,7 +4412,7 @@ class SPV_Op<string mnemonic, list<Trait> traits = []> :
// Availability specification for this op itself.
list<Availability> availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
index 71884165e9f66..916bb55698777 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
@@ -150,9 +150,9 @@ def SPV_BitFieldInsertOp : SPV_Op<"BitFieldInsert",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
];
let arguments = (ins
@@ -222,9 +222,9 @@ def SPV_BitFieldSExtractOp : SPV_BitFieldExtractOp<"BitFieldSExtract",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
];
}
@@ -259,9 +259,9 @@ def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
];
}
@@ -299,9 +299,9 @@ def SPV_BitReverseOp : SPV_BitUnaryOp<"BitReverse", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
- Capability<[SPV_C_Shader]>
+ Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
];
}
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
index 3cafd3c4f5523..a7f3649573b6c 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
@@ -364,7 +364,7 @@ def SPV_ReturnOp : SPV_Op<"Return", [InFunctionScope, NoSideEffect,
// -----
def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> {
- let summary = "Declares that this block is not reachable in the CFG.";
+ let summary = "Behavior is undefined if this instruction is executed.";
let description = [{
This instruction must be the last instruction in a block.
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
index 8a6e31f4e96c4..413af73c506de 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
@@ -43,7 +43,7 @@ def SPV_CooperativeMatrixLengthNVOp : SPV_Op<"CooperativeMatrixLengthNV",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_NV_cooperative_matrix]>,
Capability<[SPV_C_CooperativeMatrixNV]>
];
@@ -117,7 +117,7 @@ def SPV_CooperativeMatrixLoadNVOp : SPV_Op<"CooperativeMatrixLoadNV", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_NV_cooperative_matrix]>,
Capability<[SPV_C_CooperativeMatrixNV]>
];
@@ -192,7 +192,7 @@ def SPV_CooperativeMatrixMulAddNVOp : SPV_Op<"CooperativeMatrixMulAddNV",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_NV_cooperative_matrix]>,
Capability<[SPV_C_CooperativeMatrixNV]>
];
@@ -253,7 +253,7 @@ def SPV_CooperativeMatrixStoreNVOp : SPV_Op<"CooperativeMatrixStoreNV", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_NV_cooperative_matrix]>,
Capability<[SPV_C_CooperativeMatrixNV]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
index ef38689143042..32a9aafe32f37 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
@@ -70,7 +70,7 @@ def SPV_GroupBroadcastOp : SPV_Op<"GroupBroadcast",
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Groups]>
];
@@ -126,7 +126,7 @@ def SPV_SubgroupBallotKHROp : SPV_Op<"SubgroupBallotKHR", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_KHR_shader_ballot]>,
Capability<[SPV_C_SubgroupBallotKHR]>
];
@@ -181,7 +181,7 @@ def SPV_SubgroupBlockReadINTELOp : SPV_Op<"SubgroupBlockReadINTEL", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_INTEL_subgroups]>,
Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
];
@@ -231,7 +231,7 @@ def SPV_SubgroupBlockWriteINTELOp : SPV_Op<"SubgroupBlockWriteINTEL", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_INTEL_subgroups]>,
Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
index ed66f304a38e6..1d5e20fa98b84 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
@@ -59,7 +59,7 @@ def SPV_ImageDrefGatherOp : SPV_Op<"ImageDrefGather", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Shader]>
];
@@ -125,7 +125,7 @@ def SPV_ImageQuerySizeOp : SPV_Op<"ImageQuerySize", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_ImageQuery, SPV_C_Kernel]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
index a6ec4969beeac..8123f028f4979 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td
@@ -799,7 +799,7 @@ def SPV_OrderedOp : SPV_LogicalBinaryOp<"Ordered", SPV_Float, [Commutative]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Kernel]>
];
@@ -1157,7 +1157,7 @@ def SPV_UnorderedOp : SPV_LogicalBinaryOp<"Unordered", SPV_Float, [Commutative]>
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Kernel]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td
index ab9077b82d05e..0f8516fef31f2 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td
@@ -49,7 +49,7 @@ def SPV_MatrixTimesMatrixOp : SPV_Op<"MatrixTimesMatrix", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Matrix]>
];
@@ -102,7 +102,7 @@ def SPV_MatrixTimesScalarOp : SPV_Op<"MatrixTimesScalar", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Matrix]>
];
@@ -164,7 +164,7 @@ def SPV_TransposeOp : SPV_Op<"Transpose", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Matrix]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
index e69ae9c86af8b..4d22316debeb2 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
@@ -19,10 +19,7 @@ include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
// -----
def SPV_AccessChainOp : SPV_Op<"AccessChain", [NoSideEffect]> {
- let summary = [{
- Create a pointer into a composite object that can be used with OpLoad
- and OpStore.
- }];
+ let summary = "Create a pointer into a composite object.";
let description = [{
Result Type must be an OpTypePointer. Its Type operand must be the type
@@ -164,7 +161,7 @@ def SPV_InBoundsPtrAccessChainOp : SPV_Op<"InBoundsPtrAccessChain", [NoSideEffec
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Addresses]>
];
@@ -290,7 +287,7 @@ def SPV_PtrAccessChainOp : SPV_Op<"PtrAccessChain", [NoSideEffect]> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_Addresses, SPV_C_PhysicalStorageBufferAddresses, SPV_C_VariablePointers, SPV_C_VariablePointersStorageBuffer]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
index 62077f5055cc4..2f3f2f08488d9 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
@@ -39,7 +39,7 @@ def SPV_AssumeTrueKHROp : SPV_Op<"AssumeTrueKHR", []> {
let availability = [
MinVersion<SPV_V_1_0>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[SPV_KHR_expect_assume]>,
Capability<[SPV_C_ExpectAssumeKHR]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
index 534a263ff8916..199f8dfd5d217 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
@@ -70,7 +70,7 @@ def SPV_GroupNonUniformBallotOp : SPV_Op<"GroupNonUniformBallot", []> {
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformBallot]>
];
@@ -140,7 +140,7 @@ def SPV_GroupNonUniformBroadcastOp : SPV_Op<"GroupNonUniformBroadcast",
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformBallot]>
];
@@ -190,7 +190,7 @@ def SPV_GroupNonUniformElectOp : SPV_Op<"GroupNonUniformElect", []> {
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniform]>
];
@@ -257,7 +257,7 @@ def SPV_GroupNonUniformFAddOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -317,7 +317,7 @@ def SPV_GroupNonUniformFMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -377,7 +377,7 @@ def SPV_GroupNonUniformFMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -434,7 +434,7 @@ def SPV_GroupNonUniformFMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -489,7 +489,7 @@ def SPV_GroupNonUniformIAddOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -544,7 +544,7 @@ def SPV_GroupNonUniformIMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -601,7 +601,7 @@ def SPV_GroupNonUniformSMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -658,7 +658,7 @@ def SPV_GroupNonUniformSMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -716,7 +716,7 @@ def SPV_GroupNonUniformUMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
@@ -774,7 +774,7 @@ def SPV_GroupNonUniformUMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniform
let availability = [
MinVersion<SPV_V_1_3>,
- MaxVersion<SPV_V_1_5>,
+ MaxVersion<SPV_V_1_6>,
Extension<[]>,
Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
index d52378c6f0156..ebbce903a3947 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
@@ -76,7 +76,9 @@ def SPV_ConstantOp : SPV_Op<"Constant",
[ConstantLike,
DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
NoSideEffect]> {
- let summary = "The op that declares a SPIR-V normal constant";
+ let summary = [{
+ Declare a new integer-type or floating-point-type scalar constant.
+ }];
let description = [{
This op declares a SPIR-V normal constant. SPIR-V has multiple constant
@@ -567,7 +569,10 @@ def SPV_ReferenceOfOp : SPV_Op<"mlir.referenceof", [NoSideEffect]> {
// -----
def SPV_SpecConstantOp : SPV_Op<"SpecConstant", [InModuleScope, Symbol]> {
- let summary = "The op that declares a SPIR-V specialization constant";
+ let summary = [{
+ Declare a new integer-type or floating-point-type scalar specialization
+ constant.
+ }];
let description = [{
This op declares a SPIR-V scalar specialization constant. SPIR-V has
diff --git a/mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp b/mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp
index a46bc949f6054..3c8f64419d379 100644
--- a/mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp
+++ b/mlir/lib/Target/SPIRV/SPIRVBinaryUtils.cpp
@@ -31,6 +31,7 @@ void spirv::appendModuleHeader(SmallVectorImpl<uint32_t> &header,
MIN_VERSION_CASE(3);
MIN_VERSION_CASE(4);
MIN_VERSION_CASE(5);
+ MIN_VERSION_CASE(6);
#undef MIN_VERSION_CASE
}
diff --git a/mlir/test/Dialect/SPIRV/IR/availability.mlir b/mlir/test/Dialect/SPIRV/IR/availability.mlir
index 831c6040653d1..089b70cf949bb 100644
--- a/mlir/test/Dialect/SPIRV/IR/availability.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/availability.mlir
@@ -3,7 +3,7 @@
// CHECK-LABEL: iadd
func.func @iadd(%arg: i32) -> i32 {
// CHECK: min version: v1.0
- // CHECK: max version: v1.5
+ // CHECK: max version: v1.6
// CHECK: extensions: [ ]
// CHECK: capabilities: [ ]
%0 = spv.IAdd %arg, %arg: i32
@@ -23,7 +23,7 @@ func.func @atomic_compare_exchange_weak(%ptr: !spv.ptr<i32, Workgroup>, %value:
// CHECK-LABEL: subgroup_ballot
func.func @subgroup_ballot(%predicate: i1) -> vector<4xi32> {
// CHECK: min version: v1.3
- // CHECK: max version: v1.5
+ // CHECK: max version: v1.6
// CHECK: extensions: [ ]
// CHECK: capabilities: [ [GroupNonUniformBallot] ]
%0 = spv.GroupNonUniformBallot Workgroup %predicate : vector<4xi32>
@@ -33,7 +33,7 @@ func.func @subgroup_ballot(%predicate: i1) -> vector<4xi32> {
// CHECK-LABEL: module_logical_glsl450
func.func @module_logical_glsl450() {
// CHECK: spv.module min version: v1.0
- // CHECK: spv.module max version: v1.5
+ // CHECK: spv.module max version: v1.6
// CHECK: spv.module extensions: [ ]
// CHECK: spv.module capabilities: [ [Shader] ]
spv.module Logical GLSL450 { }
@@ -43,7 +43,7 @@ func.func @module_logical_glsl450() {
// CHECK-LABEL: module_physical_storage_buffer64_vulkan
func.func @module_physical_storage_buffer64_vulkan() {
// CHECK: spv.module min version: v1.0
- // CHECK: spv.module max version: v1.5
+ // CHECK: spv.module max version: v1.6
// CHECK: spv.module extensions: [ [SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer] [SPV_KHR_vulkan_memory_model] ]
// CHECK: spv.module capabilities: [ [PhysicalStorageBufferAddresses] [VulkanMemoryModel] ]
spv.module PhysicalStorageBuffer64 Vulkan { }
diff --git a/mlir/utils/spirv/gen_spirv_dialect.py b/mlir/utils/spirv/gen_spirv_dialect.py
index 441f130106816..7b0a61c2379b9 100755
--- a/mlir/utils/spirv/gen_spirv_dialect.py
+++ b/mlir/utils/spirv/gen_spirv_dialect.py
@@ -17,6 +17,7 @@
# SPIR-V enum classes.
import itertools
+import math
import re
import requests
import textwrap
@@ -266,7 +267,7 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap):
assert not (for_op and for_cap), 'cannot set both for_op and for_cap'
DEFAULT_MIN_VERSION = 'MinVersion<SPV_V_1_0>'
- DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_5>'
+ DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_6>'
DEFAULT_CAP = 'Capability<[]>'
DEFAULT_EXT = 'Extension<[]>'
@@ -367,7 +368,6 @@ def get_case_symbol(kind_name, case_name):
kind_name = operand_kind['kind']
is_bit_enum = operand_kind['category'] == 'BitEnum'
- kind_category = 'Bit' if is_bit_enum else 'I32'
kind_acronym = ''.join([c for c in kind_name if c >= 'A' and c <= 'Z'])
name_to_case_dict = {}
@@ -386,22 +386,40 @@ def get_case_symbol(kind_name, case_name):
max_len = max([len(symbol) for (symbol, _) in kind_cases])
# Generate the definition for each enum case
- fmt_str = 'def SPV_{acronym}_{case} {colon:>{offset}} '\
- '{category}EnumAttrCase<"{symbol}", {value}>{avail}'
+ case_category = 'I32Bit' if is_bit_enum else 'I32'
+ fmt_str = 'def SPV_{acronym}_{case_name} {colon:>{offset}} '\
+ '{category}EnumAttrCase{suffix}<"{symbol}"{case_value_part}>{avail}'
case_defs = []
- for case in kind_cases:
- avail = get_availability_spec(name_to_case_dict[case[0]],
+ for case_pair in kind_cases:
+ name = case_pair[0]
+ if is_bit_enum:
+ value = int(case_pair[1], base=16)
+ else:
+ value = int(case_pair[1])
+ avail = get_availability_spec(name_to_case_dict[name],
capability_mapping,
False, kind_name == 'Capability')
+ if is_bit_enum:
+ if value == 0:
+ suffix = 'None'
+ value = ''
+ else:
+ suffix = "Bit"
+ value = ', {}'.format(int(math.log2(value)))
+ else:
+ suffix = ''
+ value = ', {}'.format(value)
+
case_def = fmt_str.format(
- category=kind_category,
+ category=case_category,
+ suffix=suffix,
acronym=kind_acronym,
- case=case[0],
- symbol=get_case_symbol(kind_name, case[0]),
- value=case[1],
+ case_name=name,
+ symbol=get_case_symbol(kind_name, name),
+ case_value_part=value,
avail=' {{\n {}\n}}'.format(avail) if avail else ';',
colon=':',
- offset=(max_len + 1 - len(case[0])))
+ offset=(max_len + 1 - len(name)))
case_defs.append(case_def)
case_defs = '\n'.join(case_defs)
@@ -417,6 +435,7 @@ def get_case_symbol(kind_name, case_name):
case_names = ',\n'.join(case_names)
# Generate the enum attribute definition
+ kind_category = 'Bit' if is_bit_enum else 'I32'
enum_attr = '''def SPV_{name}Attr :
SPV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", [
{cases}
diff --git a/mlir/utils/spirv/refresh_inst.sh b/mlir/utils/spirv/refresh_inst.sh
new file mode 100755
index 0000000000000..fe08a06d557a8
--- /dev/null
+++ b/mlir/utils/spirv/refresh_inst.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+# Script for refreshing all defined SPIR-V ops using SPIR-V spec from the
+# Internet.
+#
+# Run as:
+# ./refresh_inst.sh
+
+current_file="$(readlink -f "$0")"
+current_dir="$(dirname "$current_file")"
+
+spirv_ir_include_dir="${current_dir}/../../include/mlir/Dialect/SPIRV/IR/"
+
+for file in "${spirv_ir_include_dir}"/*; do
+ file_name="$(basename $file)"
+ if [[ $file_name == "SPIRVOps.td" ||
+ $file_name == "SPIRVCLOps.td" ||
+ $file_name == "SPIRVGLOps.td" ]]; then
+ continue
+ fi
+ if [[ $file_name =~ SPIRV.*Ops.td ]]; then
+ echo "--- refreshing $file_name ---"
+ "${current_dir}/define_inst.sh" ${file_name} Op
+ fi
+done
+
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