[Mlir-commits] [mlir] 7105512 - Support alias.scope and noalias metadata lowering on intrinsics.
Mehdi Amini
llvmlistbot at llvm.org
Wed Sep 1 10:00:01 PDT 2021
Author: Tyler Augustine
Date: 2021-09-01T16:54:20Z
New Revision: 7105512a34fa84921026f01e54ec35f21d9dc874
URL: https://github.com/llvm/llvm-project/commit/7105512a34fa84921026f01e54ec35f21d9dc874
DIFF: https://github.com/llvm/llvm-project/commit/7105512a34fa84921026f01e54ec35f21d9dc874.diff
LOG: Support alias.scope and noalias metadata lowering on intrinsics.
Builds on https://reviews.llvm.org/D107870 to support annotating intrinsics with alias.scope and noalias metadata.
Reviewed By: arpith-jacob, ftynse
Differential Revision: https://reviews.llvm.org/D109025
Added:
Modified:
mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
mlir/test/mlir-tblgen/llvm-intrinsics.td
mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td b/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
index b530c62f902ba..98168d75779e4 100644
--- a/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
+++ b/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
@@ -38,7 +38,8 @@ def ArmNeon_Dialect : Dialect {
// intrinsic.
class ArmNeon_IntrOp<string mnemonic, list<int> overloadedResults,
list<int> overloadedOperands, int numResults,
- list<OpTrait> traits = [], bit requiresAccessGroup = 0>
+ list<OpTrait> traits = [], bit requiresAccessGroup = 0,
+ bit requiresAliasScope = 0>
: LLVM_IntrOpBase</*dialect=*/ArmNeon_Dialect,
/*opName=*/"intr." # mnemonic,
/*enumName=*/"aarch64_neon_" # !subst(".", "_", mnemonic),
@@ -46,7 +47,8 @@ class ArmNeon_IntrOp<string mnemonic, list<int> overloadedResults,
/*overloadedOperands=*/overloadedOperands,
/*traits=*/traits,
/*numResults=*/numResults,
- /*requiresAccessGroup=*/requiresAccessGroup>;
+ /*requiresAccessGroup=*/requiresAccessGroup,
+ /*requiresAliasScope=*/requiresAliasScope>;
// ArmNeon dialect op that corresponds to an LLVM IR intrinsic with one
// overloaded result.
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
index a0508697ec8f8..71d418e1e9890 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
@@ -255,7 +255,7 @@ def LLVM_IntrPatterns {
class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName,
list<int> overloadedResults, list<int> overloadedOperands,
list<OpTrait> traits, int numResults,
- bit requiresAccessGroup = 0>
+ bit requiresAccessGroup = 0, bit requiresAliasScope = 0>
: LLVM_OpBase<dialect, opName, traits>,
Results<!if(!gt(numResults, 0), (outs LLVM_Type:$res), (outs))> {
string resultPattern = !if(!gt(numResults, 1),
@@ -276,6 +276,9 @@ class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName,
}] # !if(!gt(requiresAccessGroup, 0),
"moduleTranslation.setAccessGroupsMetadata(op, inst);",
"(void) inst;")
+ # !if(!gt(requiresAliasScope, 0),
+ "moduleTranslation.setAliasScopeMetadata(op, inst);",
+ "(void) inst;")
# !if(!gt(numResults, 0), "$res = inst;", "");
}
@@ -283,10 +286,11 @@ class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName,
// the intrinsic into the LLVM dialect and prefixes its name with "intr.".
class LLVM_IntrOp<string mnem, list<int> overloadedResults,
list<int> overloadedOperands, list<OpTrait> traits,
- int numResults, bit requiresAccessGroup = 0>
+ int numResults, bit requiresAccessGroup = 0,
+ bit requiresAliasScope = 0>
: LLVM_IntrOpBase<LLVM_Dialect, "intr." # mnem, !subst(".", "_", mnem),
overloadedResults, overloadedOperands, traits,
- numResults, requiresAccessGroup>;
+ numResults, requiresAccessGroup, requiresAliasScope>;
// Base class for LLVM intrinsic operations returning no results. Places the
// intrinsic into the LLVM dialect and prefixes its name with "intr.".
diff --git a/mlir/test/mlir-tblgen/llvm-intrinsics.td b/mlir/test/mlir-tblgen/llvm-intrinsics.td
index a6932b3812841..1019e36e3b2ee 100644
--- a/mlir/test/mlir-tblgen/llvm-intrinsics.td
+++ b/mlir/test/mlir-tblgen/llvm-intrinsics.td
@@ -25,6 +25,8 @@
// It has a result.
// CHECK: 1,
// It does not require an access group.
+// CHECK: 0,
+// It does not require alias scopes.
// CHECK: 0>
// CHECK: Arguments<(ins LLVM_Type, LLVM_Type
@@ -44,12 +46,37 @@
// It has a result.
// GROUPS: 1,
// It requires generation of an access group LLVM metadata.
-// GROUPS: 1>
+// GROUPS: 1,
+// It does not require alias scopes.
+// GROUPS: 0>
// It has an access group attribute.
// GROUPS: OptionalAttr<SymbolRefArrayAttr>:$access_groups
//---------------------------------------------------------------------------//
+// This checks that we can define an op that takes in alias scopes metadata.
+//
+// RUN: cat %S/../../../llvm/include/llvm/IR/Intrinsics.td \
+// RUN: | grep -v "llvm/IR/Intrinsics" \
+// RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filter=ptrmask --llvmir-intrinsics-alias-scopes-regexp=ptrmask \
+// RUN: | FileCheck --check-prefix=ALIAS %s
+
+// ALIAS-LABEL: def LLVM_ptrmask
+// ALIAS: LLVM_IntrOp<"ptrmask
+// It has no side effects.
+// ALIAS: [NoSideEffect]
+// It has a result.
+// ALIAS: 1,
+// It does not require an access group.
+// ALIAS: 0,
+// It requires generation of alias scopes LLVM metadata.
+// ALIAS: 1>
+// It has alias scopes and noalias.
+// ALIAS: OptionalAttr<SymbolRefArrayAttr>:$alias_scopes
+// ALIAS: OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes
+
+//---------------------------------------------------------------------------//
+
// This checks that the ODS we produce can be consumed by MLIR tablegen. We only
// make sure the entire process does not fail and produces some C++. The shape
// of this C++ code is tested by ODS tests.
diff --git a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
index dc76962b4d289..522832aea414c 100644
--- a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
+++ b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
@@ -44,6 +44,12 @@ static llvm::cl::opt<std::string> accessGroupRegexp(
"regexp as taking an access group metadata"),
llvm::cl::cat(IntrinsicGenCat));
+static llvm::cl::opt<std::string> aliasScopesRegexp(
+ "llvmir-intrinsics-alias-scopes-regexp",
+ llvm::cl::desc("Mark intrinsics that match the specified "
+ "regexp as taking alias.scopes and noalias metadata"),
+ llvm::cl::cat(IntrinsicGenCat));
+
// Used to represent the indices of overloadable operands/results.
using IndicesTy = llvm::SmallBitVector;
@@ -196,6 +202,10 @@ static bool emitIntrinsic(const llvm::Record &record, llvm::raw_ostream &os) {
bool requiresAccessGroup =
!accessGroupRegexp.empty() && accessGroupMatcher.match(record.getName());
+ llvm::Regex aliasScopesMatcher(aliasScopesRegexp);
+ bool requiresAliasScopes =
+ !aliasScopesRegexp.empty() && aliasScopesMatcher.match(record.getName());
+
// Prepare strings for traits, if any.
llvm::SmallVector<llvm::StringRef, 2> traits;
if (intr.isCommutative())
@@ -208,6 +218,10 @@ static bool emitIntrinsic(const llvm::Record &record, llvm::raw_ostream &os) {
"LLVM_Type");
if (requiresAccessGroup)
operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$access_groups");
+ if (requiresAliasScopes) {
+ operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$alias_scopes");
+ operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes");
+ }
// Emit the definition.
os << "def LLVM_" << intr.getProperRecordName() << " : " << opBaseClass
@@ -218,7 +232,8 @@ static bool emitIntrinsic(const llvm::Record &record, llvm::raw_ostream &os) {
os << ", ";
printBracketedRange(traits, os);
os << ", " << intr.getNumResults() << ", "
- << (requiresAccessGroup ? "1" : "0") << ">, Arguments<(ins"
+ << (requiresAccessGroup ? "1" : "0") << ", "
+ << (requiresAliasScopes ? "1" : "0") << ">, Arguments<(ins"
<< (operands.empty() ? "" : " ");
llvm::interleaveComma(operands, os);
os << ")>;\n\n";
More information about the Mlir-commits
mailing list