[Mlir-commits] [mlir] e0a88db - Fix some typos.

[llvmlistbot at llvm.org]

Author: Benoit Jacob
Date: 2021-05-14T21:34:09+05:30
New Revision: e0a88db545b6ddd7bcde85502ab0fa4c393b7164

URL: https://github.com/llvm/llvm-project/commit/e0a88db545b6ddd7bcde85502ab0fa4c393b7164
DIFF: https://github.com/llvm/llvm-project/commit/e0a88db545b6ddd7bcde85502ab0fa4c393b7164.diff

LOG: Fix some typos.

Fix some typos

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102503

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
    mlir/test/Target/LLVMIR/arm-neon.mlir

Removed: 
    


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diff  --git a/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td b/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
index d57337bc8253c..a9d9f6f539dd4 100644
--- a/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
+++ b/mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
@@ -108,7 +108,7 @@ def SdotOp : ArmNeon_OverloadedOperandsWithOneResultIntrOp<"sdot",[1], [
   }];
   // Supports either:
   //   (vector<2xi32>, vector<8xi8>, vector<8xi8>) -> vector<2xi32>
-  //   (vector<4xi32>, vector<16xi8>, vector<16xi8>) -> vector<16xi32>
+  //   (vector<4xi32>, vector<16xi8>, vector<16xi8>) -> vector<4xi32>
   let arguments = (ins VectorOfLengthAndType<[4, 2], [I32]>:$a,
                        VectorOfLengthAndType<[16, 8], [I8]>:$b,
                        VectorOfLengthAndType<[16, 8], [I8]>:$c);

diff  --git a/mlir/test/Target/LLVMIR/arm-neon.mlir b/mlir/test/Target/LLVMIR/arm-neon.mlir
index d99f573c8bec0..a72a3820b2c77 100644
--- a/mlir/test/Target/LLVMIR/arm-neon.mlir
+++ b/mlir/test/Target/LLVMIR/arm-neon.mlir
@@ -24,16 +24,16 @@ llvm.func @arm_neon_smull(%arg0: vector<8xi8>, %arg1: vector<8xi8>) -> !llvm.str
   llvm.return %8 : !llvm.struct<(vector<8xi16>, vector<4xi32>, vector<2xi64>)>
 }
 
-// CHECK-LABEL: arm_neon_sdot_i8i8
-llvm.func @arm_neon_sdot_i8i8(%a: vector<2xi32>, %b: vector<8xi8>, %c: vector<8xi8>) -> vector<2xi32> {
+// CHECK-LABEL: arm_neon_sdot_8_i8i8
+llvm.func @arm_neon_sdot_8_i8i8(%a: vector<2xi32>, %b: vector<8xi8>, %c: vector<8xi8>) -> vector<2xi32> {
   // CHECK: %[[V0:.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %{{.*}}, <8 x i8> %{{.*}}, <8 x i8> %{{.*}})
   // CHECK-NEXT: ret <2 x i32>
   %0 = arm_neon.intr.sdot %a, %b, %c : vector<8xi8>, vector<8xi8> to vector<2xi32>
   llvm.return %0 : vector<2xi32>
 }
 
-// CHECK-LABEL: arm_neon_sdot_i16i16
-llvm.func @arm_neon_sdot_i16i16(%a: vector<4xi32>, %b: vector<16xi8>, %c: vector<16xi8>) -> vector<4xi32> {
+// CHECK-LABEL: arm_neon_sdot_16_i8i8
+llvm.func @arm_neon_sdot_16_i8i8(%a: vector<4xi32>, %b: vector<16xi8>, %c: vector<16xi8>) -> vector<4xi32> {
   // CHECK: %[[V0:.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
   // CHECK-NEXT: ret <4 x i32>
   %0 = arm_neon.intr.sdot %a, %b, %c : vector<16xi8>, vector<16xi8> to vector<4xi32>