[Mlir-commits] [mlir] 6c9fbcf - [mlir] Linalg: add tile interchange flag to test-linalg-codegen-strategy pass

[Eugene Zhulenev]

Author: Eugene Zhulenev
Date: 2021-03-30T10:48:34-07:00
New Revision: 6c9fbcf5b1cb6d2e0fb4a518f8c61a5eebfe6021

URL: https://github.com/llvm/llvm-project/commit/6c9fbcf5b1cb6d2e0fb4a518f8c61a5eebfe6021
DIFF: https://github.com/llvm/llvm-project/commit/6c9fbcf5b1cb6d2e0fb4a518f8c61a5eebfe6021.diff

LOG: [mlir] Linalg: add tile interchange flag to test-linalg-codegen-strategy pass

Interchange options was missing in the pass flags.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D99397

Added: 
    

Modified: 
    mlir/test/Dialect/Linalg/codegen-strategy.mlir
    mlir/test/lib/Transforms/TestLinalgCodegenStrategy.cpp

Removed: 
    


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diff  --git a/mlir/test/Dialect/Linalg/codegen-strategy.mlir b/mlir/test/Dialect/Linalg/codegen-strategy.mlir
index 5affbdccaf68f..e08d99eb03ef9 100644
--- a/mlir/test/Dialect/Linalg/codegen-strategy.mlir
+++ b/mlir/test/Dialect/Linalg/codegen-strategy.mlir
@@ -1,5 +1,6 @@
 // Test that both anchor-op name and MatmulOp-based codegen strategy produce the same result.
 // RUN: mlir-opt %s -test-linalg-codegen-strategy="tile-sizes=2,4,8 vectorize vectorize-contraction-to=matrixintrinsics unroll-vector-transfers=true" | FileCheck %s
+// RUN: mlir-opt %s -test-linalg-codegen-strategy="tile-sizes=2,4,8 tile-interchange=1,2,0 vectorize vectorize-contraction-to=matrixintrinsics unroll-vector-transfers=true" | FileCheck %s
 // RUN: mlir-opt %s -test-linalg-codegen-strategy="tile-sizes=16,32,64 promote promote-full-tile-pad register-tile-sizes=2,4,8 vectorize vectorize-contraction-to=outerproduct split-transfers=true unroll-vector-transfers=false" | FileCheck %s --check-prefix=OUTER
 // RUN: mlir-opt %s -test-linalg-codegen-strategy="anchor-op=linalg.matmul tile-sizes=2,4,8 vectorize vectorize-contraction-to=matrixintrinsics unroll-vector-transfers=true" | FileCheck %s
 // RUN: mlir-opt %s -test-linalg-codegen-strategy="anchor-op=linalg.matmul tile-sizes=16,32,64 promote promote-full-tile-pad register-tile-sizes=2,4,8 vectorize vectorize-contraction-to=outerproduct split-transfers=true unroll-vector-transfers=false" | FileCheck %s --check-prefix=OUTER

diff  --git a/mlir/test/lib/Transforms/TestLinalgCodegenStrategy.cpp b/mlir/test/lib/Transforms/TestLinalgCodegenStrategy.cpp
index 11a22bde9aac1..fc9283559d146 100644
--- a/mlir/test/lib/Transforms/TestLinalgCodegenStrategy.cpp
+++ b/mlir/test/lib/Transforms/TestLinalgCodegenStrategy.cpp
@@ -57,6 +57,10 @@ struct TestLinalgCodegenStrategy
   ListOption<int64_t> tileSizes{*this, "tile-sizes",
                                 llvm::cl::MiscFlags::CommaSeparated,
                                 llvm::cl::desc("Specifies the tile sizes.")};
+  ListOption<unsigned> tileInterchange{
+      *this, "tile-interchange", llvm::cl::MiscFlags::CommaSeparated,
+      llvm::cl::desc("Specifies the tile interchange.")};
+
   Option<bool> promote{
       *this, "promote",
       llvm::cl::desc("Promote the tile into a small aligned memory buffer."),
@@ -187,6 +191,8 @@ void TestLinalgCodegenStrategy::runOnFunction() {
   LinalgTilingOptions tilingOptions;
   if (!tileSizes.empty())
     tilingOptions = tilingOptions.setTileSizes(tileSizes);
+  if (!tileInterchange.empty())
+    tilingOptions = tilingOptions.setInterchange(tileInterchange);
 
   LinalgTilingOptions registerTilingOptions;
   if (!registerTileSizes.empty())