[Mlir-commits] [mlir] dd4fb7c - [mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Wed Sep 30 09:24:28 PDT 2020
Author: Valentin Clement
Date: 2020-09-30T12:24:21-04:00
New Revision: dd4fb7c8cfe394a3290bd19a1eac03435472ccfa
URL: https://github.com/llvm/llvm-project/commit/dd4fb7c8cfe394a3290bd19a1eac03435472ccfa
DIFF: https://github.com/llvm/llvm-project/commit/dd4fb7c8cfe394a3290bd19a1eac03435472ccfa.diff
LOG: [mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests
Switch to a dummy op in the test dialect so we can remove the -allow-unregistred-dialect
on ops.mlir and invalid.mlir. Change after comment on D88272.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D88587
Added:
Modified:
mlir/test/Dialect/OpenACC/invalid.mlir
mlir/test/Dialect/OpenACC/ops.mlir
Removed:
################################################################################
diff --git a/mlir/test/Dialect/OpenACC/invalid.mlir b/mlir/test/Dialect/OpenACC/invalid.mlir
index c56ccdb186f9..be0b0ce61152 100644
--- a/mlir/test/Dialect/OpenACC/invalid.mlir
+++ b/mlir/test/Dialect/OpenACC/invalid.mlir
@@ -1,8 +1,8 @@
-// RUN: mlir-opt -allow-unregistered-dialect -split-input-file -verify-diagnostics %s
+// RUN: mlir-opt -split-input-file -verify-diagnostics %s
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -10,7 +10,7 @@ acc.loop gang {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop worker {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -18,7 +18,7 @@ acc.loop worker {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -26,7 +26,7 @@ acc.loop vector {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang worker {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -34,7 +34,7 @@ acc.loop gang worker {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -42,7 +42,7 @@ acc.loop gang vector {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop worker vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -50,7 +50,7 @@ acc.loop worker vector {
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang worker vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq}
@@ -147,7 +147,7 @@ acc.loop {
// -----
acc.loop {
- "some.op"() ({
+ "test.openacc_dummy_op"() ({
// expected-error at +1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown
}) : () -> ()
diff --git a/mlir/test/Dialect/OpenACC/ops.mlir b/mlir/test/Dialect/OpenACC/ops.mlir
index 7ed4340fa308..e24b57245e1d 100644
--- a/mlir/test/Dialect/OpenACC/ops.mlir
+++ b/mlir/test/Dialect/OpenACC/ops.mlir
@@ -1,8 +1,8 @@
-// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | FileCheck %s
+// RUN: mlir-opt -split-input-file %s | FileCheck %s
// Verify the printed output can be parsed.
-// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
+// RUN: mlir-opt -split-input-file %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
// Verify the generic form can be parsed.
-// RUN: mlir-opt -split-input-file -allow-unregistered-dialect -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
+// RUN: mlir-opt -split-input-file -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x10xf32>) -> memref<10x10xf32> {
%c0 = constant 0 : index
@@ -203,59 +203,59 @@ func @testloopop() -> () {
%idxValue = constant 8 : index
acc.loop gang worker vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop gang(num=%i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop gang(static=%i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop worker(%i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop worker(%i32Value: i32) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop worker(%idxValue: index) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop vector(%i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop vector(%i32Value: i32) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop vector(%idxValue: index) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop gang(num=%i64Value: i64) worker vector {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop gang(num=%i64Value: i64, static=%i64Value: i64) worker(%i64Value: i64) vector(%i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop gang(num=%i32Value: i32, static=%idxValue: index) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop tile(%i64Value: i64, %i64Value: i64) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
acc.loop tile(%i32Value: i32, %i32Value: i32) {
- "some.op"() : () -> ()
+ "test.openacc_dummy_op"() : () -> ()
acc.yield
}
return
@@ -265,59 +265,59 @@ func @testloopop() -> () {
// CHECK-NEXT: [[I32VALUE:%.*]] = constant 128 : i32
// CHECK-NEXT: [[IDXVALUE:%.*]] = constant 8 : index
// CHECK: acc.loop gang worker vector {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop gang(static=[[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop worker([[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop worker([[I32VALUE]]: i32) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop worker([[IDXVALUE]]: index) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop vector([[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop vector([[I32VALUE]]: i32) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop vector([[IDXVALUE]]: index) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) worker vector {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64, static=[[I64VALUE]]: i64) worker([[I64VALUE]]: i64) vector([[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I32VALUE]]: i32, static=[[IDXVALUE]]: index) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop tile([[I64VALUE]]: i64, [[I64VALUE]]: i64) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
// CHECK: acc.loop tile([[I32VALUE]]: i32, [[I32VALUE]]: i32) {
-// CHECK-NEXT: "some.op"() : () -> ()
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
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