[Mlir-commits] [mlir] fb18202 - [AMDGPU] Fix ROCm unit test memref initialization

[llvmlistbot at llvm.org]

Author: jerryyin
Date: 2020-09-17T09:48:05-07:00
New Revision: fb182028361504569ff6322bfa12b12e1ab74e30

URL: https://github.com/llvm/llvm-project/commit/fb182028361504569ff6322bfa12b12e1ab74e30
DIFF: https://github.com/llvm/llvm-project/commit/fb182028361504569ff6322bfa12b12e1ab74e30.diff

LOG: [AMDGPU] Fix ROCm unit test memref initialization

Added: 
    

Modified: 
    mlir/test/mlir-rocm-runner/vecadd.mlir
    mlir/test/mlir-rocm-runner/vector-transferops.mlir
    mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/test/mlir-rocm-runner/vecadd.mlir b/mlir/test/mlir-rocm-runner/vecadd.mlir
index df5c073f9b81..9063974d5124 100644
--- a/mlir/test/mlir-rocm-runner/vecadd.mlir
+++ b/mlir/test/mlir-rocm-runner/vecadd.mlir
@@ -17,12 +17,20 @@ func @vecadd(%arg0 : memref<?xf32>, %arg1 : memref<?xf32>, %arg2 : memref<?xf32>
 
 // CHECK: [2.46, 2.46, 2.46, 2.46, 2.46]
 func @main() {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c5 = constant 5 : index
+  %cf1dot23 = constant 1.23 : f32
   %0 = alloc() : memref<5xf32>
   %1 = alloc() : memref<5xf32>
   %2 = alloc() : memref<5xf32>
   %3 = memref_cast %0 : memref<5xf32> to memref<?xf32>
   %4 = memref_cast %1 : memref<5xf32> to memref<?xf32>
   %5 = memref_cast %2 : memref<5xf32> to memref<?xf32>
+  scf.for %i = %c0 to %c5 step %c1 {
+    store %cf1dot23, %3[%i] : memref<?xf32>
+    store %cf1dot23, %4[%i] : memref<?xf32>
+  }
   %6 = memref_cast %3 : memref<?xf32> to memref<*xf32>
   %7 = memref_cast %4 : memref<?xf32> to memref<*xf32>
   %8 = memref_cast %5 : memref<?xf32> to memref<*xf32>

diff  --git a/mlir/test/mlir-rocm-runner/vector-transferops.mlir b/mlir/test/mlir-rocm-runner/vector-transferops.mlir
index 873897011464..3d4424cc4281 100644
--- a/mlir/test/mlir-rocm-runner/vector-transferops.mlir
+++ b/mlir/test/mlir-rocm-runner/vector-transferops.mlir
@@ -44,7 +44,11 @@ func @vectransferx4(%arg0 : memref<?xf32>, %arg1 : memref<?xf32>) {
 }
 
 func @main() {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c4 = constant 4 : index
   %cf1 = constant 1.0 : f32
+  %cf1dot23 = constant 1.23 : f32
 
   %arg0 = alloc() : memref<4xf32>
   %arg1 = alloc() : memref<4xf32>
@@ -52,6 +56,11 @@ func @main() {
   %22 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
   %23 = memref_cast %arg1 : memref<4xf32> to memref<?xf32>
 
+  scf.for %i = %c0 to %c4 step %c1 {
+    store %cf1dot23, %22[%i] : memref<?xf32>
+    store %cf1dot23, %23[%i] : memref<?xf32>
+  }
+
   %cast0 = memref_cast %22 : memref<?xf32> to memref<*xf32>
   %cast1 = memref_cast %23 : memref<?xf32> to memref<*xf32>
 

diff  --git a/mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp b/mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
index 4689926be87d..d0c515ba1f03 100644
--- a/mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
+++ b/mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
@@ -16,6 +16,7 @@
 
 #include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
+#include "mlir/Conversion/SCFToStandard/SCFToStandard.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
@@ -302,6 +303,7 @@ static LogicalResult runMLIRPasses(ModuleOp m) {
   configTargetFeatures();
 
   const char gpuBinaryAnnotation[] = "rocdl.hsaco";
+  pm.addPass(createLowerToCFGPass());
   pm.addPass(createGpuKernelOutliningPass());
   auto &kernelPm = pm.nest<gpu::GPUModuleOp>();
   kernelPm.addPass(createStripDebugInfoPass());