[Mlir-commits] [mlir] 2564926 - Fix pretty printing of linalg GenericOps when there are no inputs.
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Tue Oct 20 14:58:47 PDT 2020
Author: Federico Lebrón
Date: 2020-10-20T14:58:32-07:00
New Revision: 256492677d9591c97071ce1ee4b060a2680316c5
URL: https://github.com/llvm/llvm-project/commit/256492677d9591c97071ce1ee4b060a2680316c5
DIFF: https://github.com/llvm/llvm-project/commit/256492677d9591c97071ce1ee4b060a2680316c5.diff
LOG: Fix pretty printing of linalg GenericOps when there are no inputs.
Differential Revision: https://reviews.llvm.org/D89825
Added:
Modified:
mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
mlir/test/Dialect/Linalg/roundtrip.mlir
Removed:
################################################################################
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index 47552c31007f..cd471d5b1648 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -1453,7 +1453,8 @@ static void printNamedStructuredOpResults(OpAsmPrinter &p,
template <typename NamedStructuredOpType>
static void printCommonStructuredOpParts(OpAsmPrinter &p,
NamedStructuredOpType op) {
- p << " ins(" << op.inputs() << " : " << op.inputs().getTypes() << ")";
+ if (!op.inputs().empty())
+ p << " ins(" << op.inputs() << " : " << op.inputs().getTypes() << ")";
if (!op.output_buffers().empty())
p << " outs(" << op.output_buffers() << " : "
<< op.output_buffers().getTypes() << ")";
diff --git a/mlir/test/Dialect/Linalg/roundtrip.mlir b/mlir/test/Dialect/Linalg/roundtrip.mlir
index b4347ca89887..b63c26f21583 100644
--- a/mlir/test/Dialect/Linalg/roundtrip.mlir
+++ b/mlir/test/Dialect/Linalg/roundtrip.mlir
@@ -341,6 +341,24 @@ func @generic_with_tensor_input(%arg0: tensor<?x?xvector<3x4xi4>>,
// -----
+#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
+func @generic_without_inputs(%arg0 : memref<?x?x?xf32>) {
+ linalg.generic {indexing_maps = [#map0],
+ iterator_types = ["parallel", "parallel", "parallel"]}
+ outs(%arg0 : memref<?x?x?xf32>) {
+ ^bb0(%arg3: f32): // no predecessors
+ %cst = constant 0.000000e+00 : f32
+ linalg.yield %cst : f32
+ }
+ return
+}
+
+// CHECK-LABEL: func @generic_without_inputs
+// CHECK: linalg.generic
+// CHECK-NOT: ins
+
+// -----
+
#accesses = [
affine_map<(i, j, k) -> (j, i)>,
affine_map<(i, j, k) -> (i, k, i + j)>,
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