[Mlir-commits] [mlir] be15284 - [MLIR][StdToSPIRV] Fixed a typo in	ops conversion tests
    George Mitenkov 
    llvmlistbot at llvm.org
       
    Tue Jul 14 11:46:31 PDT 2020
    
    
  
Author: George Mitenkov
Date: 2020-07-14T21:46:07+03:00
New Revision: be15284ef60c6af8ff7ae1dad59491993a9bf6ab
URL: https://github.com/llvm/llvm-project/commit/be15284ef60c6af8ff7ae1dad59491993a9bf6ab
DIFF: https://github.com/llvm/llvm-project/commit/be15284ef60c6af8ff7ae1dad59491993a9bf6ab.diff
LOG: [MLIR][StdToSPIRV] Fixed a typo in ops conversion tests
Fixed a typo in `std-ops-to-spitv.mlir` test.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D83791
Added: 
    
Modified: 
    mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
Removed: 
    
################################################################################
diff  --git a/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir b/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
index a93bf792b34f..735223755396 100644
--- a/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
+++ b/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
@@ -181,7 +181,6 @@ module attributes {
      max_compute_workgroup_size = dense<[128, 128, 64]> : vector<3xi32>}>
 } {
 
-// CHECK-LEBEL: @int_vector4_invalid
 func @int_vector4_invalid(%arg0: vector<4xi64>) {
   // expected-error @+2 {{bitwidth emulation is not implemented yet on unsigned op}}
   // expected-error @+1 {{op requires the same type for all operands and results}}
        
    
    
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