[Mlir-commits] [mlir] 890d5e2 - [MLIR][GPU] Disallow llvm tanh intrinsics when lowering to NVVM/ROCm.
Stephan Herhut
llvmlistbot at llvm.org
Tue Feb 11 06:12:12 PST 2020
Author: Stephan Herhut
Date: 2020-02-11T15:09:30+01:00
New Revision: 890d5e2dd232f43842d8a9025e639027946d81f4
URL: https://github.com/llvm/llvm-project/commit/890d5e2dd232f43842d8a9025e639027946d81f4
DIFF: https://github.com/llvm/llvm-project/commit/890d5e2dd232f43842d8a9025e639027946d81f4.diff
LOG: [MLIR][GPU] Disallow llvm tanh intrinsics when lowering to NVVM/ROCm.
Summary:
The lowering to NVVM and ROCm handles tanh operations differently by
mapping them to NVVM/ROCm specific intrinsics. This conflicts with
the lowering to LLVM, which uses the default llvm intrinsic. This change
declares the LLVM intrinsics to be illegal, hence disallowing the
correspondign rewrite.
Differential Revision: https://reviews.llvm.org/D74389
Added:
Modified:
mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Removed:
################################################################################
diff --git a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
index 570f956ee4e9..059bdfb1661f 100644
--- a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
@@ -95,6 +95,24 @@ struct OpToFuncCallLowering : public LLVMOpLowering {
const std::string f64Func;
};
+namespace gpu {
+/// Returns a predicate to be used with addDynamicallyLegalOp. The predicate
+/// returns false for calls to the provided intrinsics and true otherwise.
+inline std::function<bool(Operation *)>
+filterIllegalLLVMIntrinsics(ArrayRef<StringRef> intrinsics, MLIRContext *ctx) {
+ SmallVector<StringRef, 4> illegalIds(intrinsics.begin(), intrinsics.end());
+ return [illegalIds](Operation *op) -> bool {
+ LLVM::CallOp callOp = dyn_cast<LLVM::CallOp>(op);
+ if (!callOp || !callOp.callee())
+ return true;
+ StringRef callee = callOp.callee().getValue();
+ return !llvm::any_of(illegalIds, [callee](StringRef intrinsic) {
+ return callee.equals(intrinsic);
+ });
+ };
+}
+} // namespace gpu
+
} // namespace mlir
#endif // MLIR_CONVERSION_GPUCOMMON_OPTOFUNCCALLLOWERING_H_
diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
index 09fbd3095168..d9f37dbf0d8c 100644
--- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
@@ -695,6 +695,8 @@ class LowerGpuOpsToNVVMOpsPass
target.addIllegalOp<FuncOp>();
target.addLegalDialect<LLVM::LLVMDialect>();
target.addLegalDialect<NVVM::NVVMDialect>();
+ target.addDynamicallyLegalOp<mlir::LLVM::CallOp>(
+ gpu::filterIllegalLLVMIntrinsics({"tanh", "tanhf"}, m.getContext()));
// TODO(csigg): Remove once we support replacing non-root ops.
target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
if (failed(applyPartialConversion(m, target, patterns, &converter)))
diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
index d74fcdbf0507..0fd8be01f15a 100644
--- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
@@ -65,8 +65,9 @@ class LowerGpuOpsToROCDLOpsPass
target.addLegalDialect<LLVM::LLVMDialect, ROCDL::ROCDLDialect>();
target.addIllegalOp<LLVM::FAbsOp, LLVM::FCeilOp, LLVM::CosOp,
LLVM::ExpOp>();
- target.addDynamicallyLegalOp<FuncOp>(
- [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); });
+ target.addDynamicallyLegalOp<LLVM::CallOp>(
+ gpu::filterIllegalLLVMIntrinsics({"tanh", "tanhf"}, m.getContext()));
+ target.addIllegalOp<FuncOp>();
if (failed(applyPartialConversion(m, target, patterns, &converter)))
signalPassFailure();
}
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